公开(公告)号：US09716181B2

公开(公告)日：2017-07-25

申请号：US15176611

申请日：2016-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Phil Ouk Nam ,  Yong-Hoon Son ,  Kyunghyun Kim ,  Byeongju Kim ,  Kwangchul Park ,  Yeon-Sil Sohn ,  Jin-l Lee ,  JongHeun Lim ,  Wonbong Jung

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78672 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1207 ,  H01L29/78642

Abstract: A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.

公开(公告)号：US20170207066A1

公开(公告)日：2017-07-20

申请号：US15133989

申请日：2016-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijong PARK ,  Jun-Youl Yang ,  Yongsun Ko ,  Kyunghyun Kim ,  Taeheon Kim ,  Jae Jin Shin

IPC: H01J37/32

CPC classification number: H01J37/32009 ,  H01J37/32449 ,  H01J37/32899 ,  H01J37/32926 ,  H01J37/32935 ,  H01J37/3299 ,  H01J2237/334

Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

公开(公告)号：US08785901B2

公开(公告)日：2014-07-22

申请号：US13875731

申请日：2013-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Jeong ,  Sukhun Choi ,  Jangeun Lee ,  Kyunghyun Kim ,  Sechung Oh ,  Kyungtae Nam

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/10 ,  H01L21/768 ,  H01L49/02 ,  H01L43/12

CPC classification number: H01L28/20 ,  H01L21/7684 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.

Abstract translation: 提供了制造半导体器件的方法，包括在衬底上形成电介质中间层，电介质层间限定开口。 在开口中形成金属图案。 对金属图案进行氧化处理以形成导电金属氧化物图案，并且导电金属氧化物图案被平坦化。 还提供了相关的半导体器件。

公开(公告)号：US12287452B2

公开(公告)日：2025-04-29

申请号：US17709837

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmun Choi ,  Kyunghyun Kim ,  Hyunsuk Choi

IPC: G02B1/115 ,  G02B5/00

Abstract: An electronic device and ornamental member for the same are disclosed herein. The electronic devices includes a housing, a front plate disposed on one surface of the housing, and a rear plate disposed on a rear surface of the housing, wherein one of the plates includes the ornamental member, which includes: a base film attached to one surface of a transparent plate and configured to at least partially transmit light, an ultra-violet (UV) molding layer formed on a surface of the base film, and a plurality of refractive layers sequentially stacked on a surface of the UV molding layer, wherein at least one of the plurality of refractive layers is formed to have a different refractive index and a different surface area from a remainder of the refractive layers.

公开(公告)号：US10103163B2

公开(公告)日：2018-10-16

申请号：US15249389

申请日：2016-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jin-I Lee ,  Kyunghyun Kim ,  Byeongju Kim ,  Phil Ouk Nam ,  Kwangchul Park ,  Yeon-Sil Sohn ,  JongHeun Lim ,  Wonbong Jung

IPC: H01L29/41 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.

公开(公告)号：US20150348799A1

公开(公告)日：2015-12-03

申请号：US14824786

申请日：2015-08-12

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Young Taek Hong ,  Jinuk Lee ,  Junghun Lim ,  Jaewan Park ,  Chanjin Jeong ,  Hoon Han ,  Seonghwan Park ,  Yanghwa Lee ,  Sang Won Bae ,  Daehong Eom ,  Byoungmoon Yoon ,  Jihoon Jeong ,  Kyunghyun Kim ,  Kyounghwan Kim ,  ChangSup Mun ,  Se-Ho Cha ,  Yongsun Ko

IPC: H01L21/311 ,  H01L27/115 ,  H01L29/66 ,  C09K13/06

CPC classification number: H01L29/7926 ,  C09K13/04 ,  C09K13/06 ,  C23F1/16 ,  H01L21/31111 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889

Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Abstract translation: 提供蚀刻组合物。 蚀刻组合物包括磷酸，铵离子和硅化合物材料。 硅化合物材料包括硅原子，选自氮原子，磷原子和与硅原子结合的硫原子中的至少一种，以及与硅原子结合的至少两个氧原子。 还提供了利用蚀刻组合物的方法。

公开(公告)号：US20240074076A1

公开(公告)日：2024-02-29

申请号：US18240136

申请日：2023-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Poonggi JUNG ,  Seonjung Kim ,  Kyunghyun Kim ,  Hakju Kim ,  Hyunsuk Choi

IPC: H05K5/02

CPC classification number: H05K5/0243

Abstract: A housing of an electronic device includes a base layer, a first visible layer provided on a first surface of the base layer, and a second visible layer provided on a second surface of the base layer. The second visible layer is non-visible from an outside of the electronic device in a first illumination environment and where the first visible layer and the second visible layer are visible from the outside of the electronic device in a second illumination environment.

公开(公告)号：US20230230843A1

公开(公告)日：2023-07-20

申请号：US18095798

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeheon Kim ,  Kyunghyun Kim ,  Changsup Mun ,  Junyoul Yang ,  Sanghoon Jeong ,  Yongsik Chung ,  Seungcheol Chae

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L21/31111 ,  H01L29/66666 ,  H10B80/00

Abstract: A wet etching method includes: providing a structure including an etching target film into a process bath containing a first etching solution having a first phosphoric acid concentration; performing a first etching process for etching the etching target film with the first etching solution in the process bath; providing a second etching solution having a second phosphoric acid concentration different from the first phosphoric acid concentration by changing a phosphoric acid concentration in the first etching solution; performing a second etching process for etching the etching target film with the second etching solution in the process bath; providing a third etching solution having a third phosphoric acid concentration different from the first and second phosphoric acid concentrations by changing a phosphoric acid concentration in the second etching solution; and performing a third etching process for etching the etching target film with the third etching solution in the process bath.

公开(公告)号：US10580617B2

公开(公告)日：2020-03-03

申请号：US15841230

申请日：2017-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijong Park ,  Jun-Youl Yang ,  Yongsun Ko ,  Kyunghyun Kim ,  Taeheon Kim ,  Jae Jin Shin

IPC: H01J37/32

Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

公开(公告)号：US20160307773A1

公开(公告)日：2016-10-20

申请号：US14990353

申请日：2016-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mongsup Lee ,  Yoonho Son ,  Sang-Jun Lee ,  Munkwon Kang ,  Kyunghyun Kim ,  Inseak Hwang

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/02063 ,  H01L21/7682 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100° C. or more during the removal process.

Abstract translation: 具有包含氧化物的绝缘层的衬底被加载到腔室中，并且通过将包括蚀刻源气体的处理气体注入到室中来去除绝缘层的至少一部分。 去除处理以多次重复第一周期和第二周期的脉冲类型执行。 蚀刻源气体在第一时段期间以第一流量供应，并且在第二时段期间以小于第一流量的第二流量供应。 在除去过程中，室内温度保持在100℃或更高。