公开(公告)号：US20130256771A1

公开(公告)日：2013-10-03

申请号：US13900581

申请日：2013-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue

IPC: H01L27/108

CPC classification number: H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Abstract translation: 半导体器件包括源极线，位线，信号线，字线，在源极线和位线之间并联连接的存储器单元，通过开关电连接到源极线和位线的第一驱动器电路 元件，通过开关元件电连接到源极线的第二驱动器电路，电连接到信号线的第三驱动电路，以及电连接到字线的第四驱动电路。 存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。 第二晶体管包括氧化物半导体材料。

公开(公告)号：US20130228838A1

公开(公告)日：2013-09-05

申请号：US13861681

申请日：2013-04-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: H01L27/108

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US20130135185A1

公开(公告)日：2013-05-30

申请号：US13688789

申请日：2012-11-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Tomoaki Atsumi ,  Jun Koyama

IPC: G09G3/36

CPC classification number: G09G3/36 ,  G09G3/3648 ,  G09G2360/144

Abstract: A display device driver circuit in which a lookup table can be written into a memory circuit within a retrace period even when the lookup table is constantly reconstructed in accordance with a change in the external environment and stored in the memory circuit, and data of the lookup table can be held even if supply of power supply voltage stops. In a driver circuit for a display device, a memory circuit including a transistor having a semiconductor layer containing an oxide semiconductor is used as a memory circuit that stores a lookup table for correcting image signals in accordance with a change in the external environment.

Abstract translation: 一种显示设备驱动器电路，其中即使当根据外部环境的变化并且存储在存储器电路中不断重建查找表时，也可以在回扫周期内将查找表写入存储器电路中，并且查找数据 即使电源电压供应停止，也可以保持工作台。 在用于显示装置的驱动器电路中，使用包括具有包含氧化物半导体的半导体层的晶体管的存储电路作为存储电路，其存储根据外部环境的变化来校正图像信号的查找表。

公开(公告)号：US12101945B2

公开(公告)日：2024-09-24

申请号：US18225186

申请日：2023-07-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC: H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/408 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70

CPC classification number: H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/7869 ,  H10B41/20 ,  H10B41/70

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US11929470B2

公开(公告)日：2024-03-12

申请号：US18127072

申请日：2023-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Akihiro Kimura

IPC: H02J7/00 ,  H01M10/44 ,  H02J50/10 ,  H02J50/27 ,  H02J50/40 ,  H04B1/3883

CPC classification number: H01M10/44 ,  H02J7/00 ,  H02J50/10 ,  H02J50/27 ,  H02J50/402 ,  H04B1/3883

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US11062762B2

公开(公告)日：2021-07-13

申请号：US16796140

申请日：2020-02-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Shuhei Nagatsuka

IPC: G11C11/40 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/10 ,  G11C11/405 ,  H01L27/108 ,  G11C11/401 ,  G11C16/04 ,  G11C16/08 ,  G11C16/28 ,  G11C11/4091

Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.

公开(公告)号：US10923477B2

公开(公告)日：2021-02-16

申请号：US16484577

申请日：2018-02-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Yuta Endo ,  Shuhei Nagatsuka

IPC: H01L29/786 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L21/027 ,  H01L21/465

Abstract: A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and the second conductor and in contact with the third region and the fourth region.

公开(公告)号：US10573374B2

公开(公告)日：2020-02-25

申请号：US15784495

申请日：2017-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Shuhei Nagatsuka

IPC: G11C11/40 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/10 ,  G11C11/405 ,  H01L27/108 ,  G11C16/04 ,  G11C16/08 ,  G11C16/28

Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.

公开(公告)号：US10109371B2

公开(公告)日：2018-10-23

申请号：US15391929

申请日：2016-12-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Kazuaki Ohshima

IPC: G11C11/22 ,  G11C29/50 ,  G11C11/4096 ,  H01L27/108

Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

公开(公告)号：US09741400B2

公开(公告)日：2017-08-22

申请号：US15341707

申请日：2016-11-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Tomokazu Yokoi ,  Naoaki Tsutsui ,  Kazuaki Ohshima ,  Tatsuya Onuki

IPC: G11C7/10 ,  G11C7/06 ,  H01L27/11582 ,  H01L27/11568 ,  G11C5/06 ,  G11C8/10 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.