公开(公告)号：US09900996B2

公开(公告)日：2018-02-20

申请号：US14453977

申请日：2014-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Ko-Cheng Liu ,  Fu-Tang Huang

IPC: H05K1/00 ,  H05K3/46 ,  H05K1/09 ,  H05K1/18 ,  H05K1/02 ,  H05K3/28

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/181 ,  H05K1/02 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/0191 ,  H05K2201/09736 ,  H05K2201/20 ,  H05K2203/0353 ,  H05K2203/0369 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.

公开(公告)号：US20170207161A1

公开(公告)日：2017-07-20

申请号：US15352856

申请日：2016-11-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

公开(公告)号：US09520351B2

公开(公告)日：2016-12-13

申请号：US14564145

申请日：2014-12-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Ko-Cheng Liu ,  Fu-Tang Huang

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/02 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L23/3121 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/181 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/0195 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.

Abstract translation: 提供了一种封装基板和封装结构。 包装衬底包括多个电介质层，其中两个具有不同的厚度; 以及与电介质层交替层叠的多个电路层。 因此，避免了现有技术中遇到的包装翘曲。

公开(公告)号：US09425152B2

公开(公告)日：2016-08-23

申请号：US14622255

申请日：2015-02-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/78 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

Abstract translation: EMI屏蔽封装结构包括具有第一表面和芯片安装区域的基板单元和与第一表面相对的第二表面，形成在第一表面上的金属柱，安装在芯片安装区域上并与之电连接的芯片， 在将所述金属柱的一部分从所述密封剂暴露出来的同时覆盖所述芯片和所述第一表面的密封剂以及封装所述密封剂并电连接到所述金属柱的屏蔽膜。 进一步提供通过两个切割工艺的上述结构的制造方法。 第一切割工艺通过切割密封剂形成凹槽。 在凹槽中形成屏蔽膜并与金属柱电连接之后，通过第二切割工艺形成完整的封装结构，从而在克服现有技术中遇到的屏蔽膜的不良接地的同时简化制造工艺。

公开(公告)号：US20150235914A1

公开(公告)日：2015-08-20

申请号：US14328092

申请日：2014-07-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Po-Hua Chen ,  Fu-Tang Huang

IPC: H01L23/13 ,  H05K3/46 ,  H05K1/11 ,  C25D5/02 ,  H01L23/00 ,  H01L21/48

CPC classification number: H05K3/4661 ,  C25D5/02 ,  C25D5/48 ,  C25D7/00 ,  H01L21/4853 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2924/3841 ,  H05K1/111 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A flip-chip packaging substrate is provided, which includes: a substrate body; a plurality of conductive pads formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having a plurality of openings correspondingly exposing a portion of each of the conductive pads; and a metal layer formed on each of the conductive pads in the openings, wherein the metal layer has a top surface having a lowest point lower than a top surface of the insulating layer, and a thickness ratio of the metal layer to the insulating layer is greater than or equal to 1/4 and less than 1, thereby preventing a solder bridge or short circuit from occurring.

Abstract translation: 提供一种倒装芯片封装基板，其包括：基板主体; 形成在所述基板主体的表面上的多个导电焊盘; 绝缘层，其形成在所述基板主体的表面上并且具有多个开口，对应地暴露所述导电焊盘的每一个的一部分; 以及形成在所述开口中的每个所述导电焊盘上的金属层，其中，所述金属层具有比所述绝缘层的顶表面低的最低点的顶表面，并且所述金属层与所述绝缘层的厚度比为 大于或等于1/4且小于1，从而防止发生焊料桥或短路。

公开(公告)号：US20150014848A1

公开(公告)日：2015-01-15

申请号：US14258361

申请日：2014-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Fu-Tang Huang

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17106 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.

Abstract translation: 公开了一种半导体器件，其包括：具有基板主体的基板和形成在基板主体上的多个导电焊盘，其中每个导电焊盘至少形成在其第一表面中的开口; 具有多个接合焊盘的半导体部件; 在所述接合焊盘和所述导电焊盘之间以及所述导电焊盘的所述开口中形成的多个导电元件; 以及形成在衬底和半导体部件之间用于封装导电元件的密封剂，从而加强导电元件和导电焊盘之间的接合，从而提高产品产量。

公开(公告)号：US11973014B2

公开(公告)日：2024-04-30

申请号：US16690801

申请日：2019-11-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/10175 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/3841 ,  H01L2224/13147 ,  H01L2924/00014

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

公开(公告)号：US20170294371A1

公开(公告)日：2017-10-12

申请号：US15499446

申请日：2017-04-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/367 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.

公开(公告)号：US20170148679A1

公开(公告)日：2017-05-25

申请号：US15424116

申请日：2017-02-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Keng-Hung Liu ,  Fu-Tang Huang

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3178 ,  H01L23/544 ,  H01L24/06 ,  H01L24/17 ,  H01L2223/54453 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner; a stopping portion formed at edges of the semiconductor element; an insulating layer formed on an active surface of the semiconductor element and the stopping portion; and an encapsulant formed between the packaging substrate and the insulating layer. The insulating layer has a recessed portion formed on the stopping portion and facing the packaging substrate such that during a reliability test, the recessed portion can prevent delamination occurring between the insulating layer and the stopping portion from extending to the active surface of the semiconductor element.

公开(公告)号：US20200091059A1

公开(公告)日：2020-03-19

申请号：US16690801

申请日：2019-11-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.