公开(公告)号：US09899521B2

公开(公告)日：2018-02-20

申请号：US15058344

申请日：2016-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sung-Li Wang ,  Ding-Kang Shih ,  Chih-Hsin Ko

IPC分类号： H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3205 ,  H01L23/485 ,  H01L29/417 ,  H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L29/06 ,  H01L21/02

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28247 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/32051 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.

公开(公告)号：US09748143B2

公开(公告)日：2017-08-29

申请号：US15253958

申请日：2016-09-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L29/15 ,  H01L29/06 ,  H01L21/3105 ,  H01L29/778 ,  H01L29/165 ,  H01L21/321 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L29/43

CPC分类号： H01L29/7842 ,  H01L21/02532 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/157 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

摘要： A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

公开(公告)号：US09601342B2

公开(公告)日：2017-03-21

申请号：US14846020

申请日：2015-09-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Chi-Wen Liu ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/161 ,  H01L27/088 ,  H01L29/165 ,  H01L21/8234 ,  H01L29/778 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/43

CPC分类号： H01L29/161 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66712 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7802 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

公开(公告)号：US20170069736A1

公开(公告)日：2017-03-09

申请号：US15357782

申请日：2016-11-21

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： You-Ru Lin ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7853

摘要： The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.

摘要翻译： 本公开提供了一种FinFET器件。 FinFET器件包括第一半导体材料的半导体衬底; 覆盖半导体衬底的第一半导体材料的鳍结构，其中鳍结构具有第一晶面取向的顶表面; 设置在所述翅片结构的顶表面上的第二半导体材料的菱形形状结构，其中所述菱形形状结构具有至少一个第二晶面取向的表面; 设置在所述菱形形状结构上的栅极结构，其中所述栅极结构分离源极区域和漏极区域; 以及在源极和漏极区域之间以菱形形状结构限定的沟道区域。

公开(公告)号：US09590068B2

公开(公告)日：2017-03-07

申请号：US14546031

申请日：2014-11-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/812

CPC分类号： H01L29/8124 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/66431 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/812

摘要： A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.

摘要翻译： 多栅极晶体管包括在衬底上的半导体鳍。 半导体鳍片包括由第一半导体材料形成的中心鳍片; 以及半导体层，其具有在中心散热片的相对侧壁上的第一部分和第二部分。 半导体层包括与第一半导体材料不同的第二半导体材料。 多栅极晶体管还包括围绕半导体鳍片的侧壁的栅电极; 以及在半导体鳍片的相对端上的源极区域和漏极区域。 中央翅片和半导体层中的每一个从源极区域延伸到漏极区域。

公开(公告)号：US09583379B2

公开(公告)日：2017-02-28

申请号：US14936372

申请日：2015-11-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsin Ko ,  Cheng-Hsien Wu ,  Clement Hsingjen Wann

IPC分类号： H01L21/00 ,  H01L29/00 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3205 ,  H01L29/20 ,  H01L29/04

CPC分类号： H01L21/76283 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/76224 ,  H01L21/76272 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/2003

摘要： A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.

摘要翻译： 提供具有外延层的半导体器件的制造方法。 半导体器件具有形成在其中的沟槽的衬底和形成在沟槽下方的凹部。 凹槽具有（111）晶体取向的侧壁。 沟槽的深度使得深度大于或等于凹部的侧壁长度的二分之一。 在凹槽和沟槽中形成外延层。 沟槽的深度足以引起在半导体衬底和外延层的界面之间形成的位错，从而沿沟槽的侧壁终止。

公开(公告)号：US09559099B2

公开(公告)日：2017-01-31

申请号：US14295278

申请日：2014-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  You-Ru Lin ,  Cheng-Tien Wan ,  Cheng-Hsien Wu ,  Chih-Hsin Ko

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L21/02694 ,  H01L21/02532 ,  H01L21/30625 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7853

摘要： A FinFET device comprises an isolation region in a substrate, wherein the isolation region comprises a plurality of non-vertical sidewalls, a first V-shaped groove, a second V-shaped groove and a third V-shaped groove formed in the substrate, a first cloak-shaped active region over the first V-shaped groove, wherein a top surface of the first cloak-shaped active region comprises a first slope, a second cloak-shaped active region over the second V-shaped groove, wherein a top surface of the second cloak-shaped active region is triangular in shape and a third cloak-shaped active region over the third V-shaped groove, wherein a top surface of the third cloak-shaped active region comprises a second slope.

摘要翻译： FinFET器件包括在衬底中的隔离区域，其中隔离区域包括多个非垂直侧壁，第一V形槽，第二V形槽和形成在衬底中的第三V形槽， 在第一V形槽上方的第一斗篷形活动区域，其中第一斗篷形活动区域的顶表面包括第一斜面，第二V形槽上方的第二斗篷形有源区域，其中顶表面 所述第二斗篷形活动区域的形状为三角形，并且在所述第三V形槽上方具有第三斗篷形有源区域，其中所述第三斗篷形有源区域的顶表面包括第二斜面。

公开(公告)号：US20160380056A1

公开(公告)日：2016-12-29

申请号：US14753916

申请日：2015-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yee-Chia Yeo ,  Chih Chieh Yeh ,  Chih-Hsin Ko ,  Cheng-Hsien Wu ,  Liang-Yin Chen ,  Xiong-Fei Yu ,  Yen-Ming Chen ,  Chan-Lon Yang

IPC分类号： H01L29/10 ,  H01L29/165 ,  H01L21/324 ,  H01L29/66

CPC分类号： H01L21/28185 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28238 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

摘要： A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.

摘要翻译： 一种方法包括在半导体鳍片上形成硅覆盖层，在硅覆盖层上形成界面层，在界面层上形成高k栅极电介质，并在高k栅极电介质上形成清除金属层。 然后在硅覆盖层，界面层，高k栅极电介质和扫气金属层上进行退火。 填充金属沉积在高k栅极电介质上。

公开(公告)号：US20160343846A1

公开(公告)日：2016-11-24

申请号：US15225298

申请日：2016-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Ching Cheng ,  Chih-Hsin Ko ,  Hsingien Wann

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L29/20 ,  H01L21/308 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28 ,  H01L29/45

摘要： A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.

摘要翻译： 公开了一种具有改进的器件性能的器件及其制造方法。 示例性器件包括III-V族化合物半导体衬底，其包括具有（110）结晶取向的表面和设置在III-V族化合物半导体衬底上的栅叠层。 栅极堆叠包括设置在具有（110）晶体取向的表面上的高k电介质层，以及设置在高k电介质层上的栅电极。

公开(公告)号：US09443769B2

公开(公告)日：2016-09-13

申请号：US14257809

申请日：2014-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sung-Li Wang ,  Neng-Kuo Chen ,  Ding-Kang Shih ,  Meng-Chun Chang ,  Yi-An Lin ,  Gin-Chen Huang ,  Chen-Feng Hsu ,  Hau-Yu Lin ,  Chih-Hsin Ko ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC分类号： H01L29/00 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823814 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858

摘要： Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the isolation region. Each of the epitaxial regions has a widest mid-region between an upper-surface and an under-surface. A dual-layer etch stop is formed over the fin structures and comprises a first sub-layer and a second sub-layer. The first sub-layer is along the upper- and under-surfaces and the isolation region. The second sub-layer is over the first sub-layer and along the upper-surfaces, and the second sub-layer merges together proximate the widest mid-regions of the epitaxial regions. Portions of the dual-layer etch stop are removed from the upper- and under-surfaces. A dielectric layer is formed on the upper- and under-surfaces. A metal layer is formed on the dielectric layer on the upper-surfaces. A barrier layer is formed on the metal layer and along the under-surfaces.

摘要翻译： 翅片结构形成在基底上。 隔离区域在翅片结构之间。 翅片结构包括在隔离区域上方延伸的外延区域。 每个外延区域在上表面和下表面之间具有最宽的中间区域。 双层蚀刻停止件形成在翅片结构之上并且包括第一子层和第二子层。 第一子层沿着上表面和下表面以及隔离区域。 第二子层在第一子层之上并且沿着上表面，并且第二子层在外延区域的最宽的中间区域附近合并在一起。 从上表面和下表面去除双层蚀刻停止件的部分。 在上表面和下表面上形成介电层。 在上表面的电介质层上形成金属层。 在金属层上和沿着底面形成阻挡层。