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    Methods for fabricating and filling conductive vias and conductive vias so formed
    11.
    发明申请
    Methods for fabricating and filling conductive vias and conductive vias so formed 有权
    制造和填充如此形成的导电通孔和导电通孔的方法

    公开(公告)号：US20070184654A1

    公开(公告)日：2007-08-09

    申请号：US11347153

    申请日：2006-02-03

    申请人： Salman Akram ,  William Hiatt ,  Steve Oliver ,  Alan Wood ,  Sidney Rigg ,  James Wark ,  Kyle Kirby

    发明人： Salman Akram ,  William Hiatt ,  Steve Oliver ,  Alan Wood ,  Sidney Rigg ,  James Wark ,  Kyle Kirby

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

    摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

    摘要翻译： 用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。 通孔可以用单个掩模形成，在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其他特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。 可以在每个通孔的表面上形成阻挡层。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。