公开(公告)号：US12046642B2

公开(公告)日：2024-07-23

申请号：US17538715

申请日：2021-11-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shinji Fujikake

IPC分类号： H01L29/16 ,  H01L21/02 ,  H01L21/324

CPC分类号： H01L29/1608 ,  H01L21/02378 ,  H01L21/324

摘要： A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first semiconductor type, a first semiconductor layer of the first semiconductor type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first semiconductor type, trenches, a gate insulating film, and gate electrodes. The silicon carbide semiconductor device has a minimum value of a subthreshold slope factor (subthreshold swing) in a subthreshold region in a range from 0.24V/dec. to 0.3V/dec.

公开(公告)号：US20240222162A1

公开(公告)日：2024-07-04

申请号：US18457240

申请日：2023-08-28

申请人： Magnachip Semiconductor, Ltd.

发明人： Jungyeon LEE ,  Seongchan JEON ,  Kihwan KIM ,  Kitae KANG ,  Jiyong LIM ,  Hohyun KIM ,  Chanho PARK

IPC分类号： H01L21/67 ,  H01L21/324 ,  H01L21/687

CPC分类号： H01L21/67115 ,  H01L21/324 ,  H01L21/67248 ,  H01L21/68764

摘要： A wafer annealing apparatus includes a gas supply unit located on one side of the wafer annealing apparatus and configured to supply high-temperature gases to transfer heat to wafers loaded inside the wafer annealing apparatus, a rotation driving unit comprising a rotation controller and configured to rotate a wafer support unit loaded with wafers, and a gas release unit located on the other side of the wafer annealing apparatus and configured to release the high-temperature gases fed to the wafer annealing apparatus. The rotation controller includes at least one processor configured to transmit a control signal to the rotation driving unit and control a rotation cycle and a rotation angle of the rotation driving unit.

公开(公告)号：US20240218503A1

公开(公告)日：2024-07-04

申请号：US18608005

申请日：2024-03-18

申请人： Applied Materials, Inc.

发明人： Sang-Ho YU ,  Kevin MORAES ,  Seshadri GANGULI ,  Hua CHUNG ,  See-Eng PHAN

IPC分类号： C23C16/16 ,  C23C16/02 ,  C23C16/18 ,  C23C16/455 ,  C23C16/50 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768

CPC分类号： C23C16/16 ,  C23C16/0218 ,  C23C16/0245 ,  C23C16/18 ,  C23C16/4554 ,  C23C16/45542 ,  C23C16/50 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/324 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76883

摘要： Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US20240213320A1

公开(公告)日：2024-06-27

申请号：US18420777

申请日：2024-01-24

申请人： SK hynix Inc.

发明人： Seong-Wan RYU

IPC分类号： H01L29/08 ,  H01L21/324 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0873 ,  H01L21/324 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.

公开(公告)号：US12009232B2

公开(公告)日：2024-06-11

申请号：US17843602

申请日：2022-06-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Wen Wu ,  Chun-Ta Chen ,  Chin-Shen Hsieh ,  Cheng-Yi Huang

IPC分类号： F27D3/00 ,  F27B17/00 ,  F27D5/00 ,  H01L21/324 ,  H01L21/67

CPC分类号： H01L21/67103 ,  F27B17/0025 ,  F27D3/0084 ,  F27D5/0037 ,  H01L21/324

摘要： In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.

公开(公告)号：US20240178004A1

公开(公告)日：2024-05-30

申请号：US18437058

申请日：2024-02-08

申请人： Applied Materials, Inc.

发明人： Pradeep SAMPATH KUMAR ,  Norman L. TAM ,  Dongming IU ,  Shashank SHARMA ,  Eric R. RIESKE ,  Michael P. KAMP

IPC分类号： H01L21/324 ,  H01L21/321 ,  H01L21/67

CPC分类号： H01L21/324 ,  H01L21/321 ,  H01L21/67098 ,  H01L21/67201

摘要： Aspects of the present disclosure relate to methods, systems, and apparatus for conducting a radical treatment operation on a substrate prior to conducting an annealing operation on the substrate. In one implementation, a method of processing semiconductor substrates includes pre-heating a substrate, and exposing the substrate to species radicals. The exposing of the substrate to the species radicals includes a treatment temperature that is less than 300 degrees Celsius, a treatment pressure that is less than 1.0 Torr, and a treatment time that is within a range of 8.0 minutes to 12.0 minutes. The method includes annealing the substrate after the exposing of the substrate to the species radicals. The annealing includes exposing the substrate to molecules, an anneal temperature that is 300 degrees Celsius or greater, an anneal pressure that is within a range of 500 Torr to 550 Torr, and an anneal time that is less than 4.0 minutes.

公开(公告)号：US20240170298A1

公开(公告)日：2024-05-23

申请号：US18495840

申请日：2023-10-27

申请人： EM Microelectronic-Marin SA

发明人： Jean-Philippe JACQUEMIN ,  Jérôme LOLIVIER ,  René MEYER

IPC分类号： H01L21/3205 ,  H01L21/324

CPC分类号： H01L21/32053 ,  H01L21/324

摘要： A method to produce an integrated circuit including depositing a first layer of a metallic chemical constituent on a silicon substrate. A protective layer including a main chemical constituent different from the main chemical constituent of the first layer is then deposited on this first layer. An additional layer is deposited on the protective layer and includes a main chemical constituent different from, equivalent to or of equivalent size to the main chemical constituent of the first layer. A heat treatment operation is carried out at a first temperature to generate a silicide including the main constituent of the first layer and silicon according to a first stoichiometry. In a subsequent step, the additional layer and the protective layer are removed. In another step, a further heat treatment operation is carried out at a temperature greater than the first temperature in order to change the stoichiometry of the previously created silicide.

公开(公告)号：US11990332B2

公开(公告)日：2024-05-21

申请号：US16637170

申请日：2018-08-06

申请人： Applied Materials, Inc.

发明人： Bhaskar Jyoti Bhuyan ,  Mark Saly ,  Zhelin Sun ,  Ning Li ,  Mihaela Balseanu ,  Li-Qun Xia ,  Yijun Liu ,  Lin Yang

IPC分类号： C23C16/455 ,  C23C16/36 ,  C23C16/56 ,  H01L21/02 ,  H01L21/324

CPC分类号： H01L21/02167 ,  C23C16/36 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/324

摘要： Methods and apparatus for forming a conformal SiCON film on a surface are described. A SiCN film is formed on a substrate surface and exposed to a low temperature steam annealing process to form a film resistant to damage by rapid thermal processing or ashing. The film is treated by rapid thermal processing and then subjected to a high temperature anneal to form a film with a low dielectric constant.

公开(公告)号：US11984490B2

公开(公告)日：2024-05-14

申请号：US17826255

申请日：2022-05-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Meng-Han Lin ,  Te-An Chen

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/285 ,  H01L21/311 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L29/66143 ,  H01L21/02063 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28537 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/47 ,  H01L29/872

摘要： A semiconductor device includes a first well region in a substrate; a first dielectric layer over the first well region, wherein the first dielectric layer includes a stepped shape over the first well region; and a conductive layer over the first well region. The conductive layer forms a Schottky barrier interface with the first well region.

公开(公告)号：US11972986B2

公开(公告)日：2024-04-30

申请号：US16981048

申请日：2019-03-13

申请人： SILTRONIC AG

发明人： Michael Boy ,  Christina Kruegler

IPC分类号： C30B33/08 ,  G01N21/21 ,  G01N21/95 ,  H01L21/324 ,  H01L21/66 ,  H01L21/67

CPC分类号： H01L22/20 ,  C30B33/08 ,  G01N21/21 ,  G01N21/9505 ,  H01L21/324 ,  H01L21/67288

摘要： Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.