公开(公告)号：US12080680B2

公开(公告)日：2024-09-03

申请号：US17898177

申请日：2022-08-29

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Makoto Mizukami ,  Tatsuya Hirakawa ,  Tomohiro Iguchi

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/83439

Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.

公开(公告)号：US12080625B2

公开(公告)日：2024-09-03

申请号：US18235668

申请日：2023-08-18

Applicant: Infineon Technologies Austria AG

Inventor： Li Fong Chong ,  Yee Beng Daryl Yeow ,  Chii Shang Hong ,  Azlina Kassim ,  Hui Kin Lit

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/433

CPC classification number: H01L23/4334 ,  H01L21/561 ,  H01L21/565 ,  H01L23/315 ,  H01L23/49503 ,  H01L23/562 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48245

Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.

公开(公告)号：US20240291439A1

公开(公告)日：2024-08-29

申请号：US18637486

申请日：2024-04-17

Applicant: NXP USA, Inc.

Inventor： Geoffrey Tucker ,  Lakshminarayan Viswanathan ,  Jeffrey Kevin Jones ,  Elie A. Maalouf

IPC: H03F1/30 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/528 ,  H03F3/21

CPC classification number: H03F1/301 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/528 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H03F3/21 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/92225 ,  H03F2200/451

Abstract: Power amplifier modules (PAMs) having topside cooling interfaces are disclosed, as are methods for fabricating such PAMs. In embodiments, the method includes attaching the RF power die to a die support-surface of a module substrate. The RF power die is attached to the module substrate in an inverted orientation such that a frontside of the RF power die faces the module substrate. When attaching the RF power die to the module substrate, a frontside input/output interface of the RF power die is electrically coupled to corresponding substrate interconnect features of the module substrate. The method further includes providing a primary heat extraction path extending from the transistor channel of the RF power die to a topside cooling interface of the PAM in a direction opposite the module substrate.

公开(公告)号：US20240290683A1

公开(公告)日：2024-08-29

申请号：US18114362

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Wen-Yi LIN ,  Kuang-Chun LEE ,  Chien-Chen LI ,  Chien-Li KUO ,  Kuo-Chio LIU

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/053 ,  H01L23/367

CPC classification number: H01L23/3732 ,  H01L21/4871 ,  H01L23/053 ,  H01L23/3672 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: An embodiment semiconductor package structure may include a package substrate, a semiconductor die coupled to the package substrate, and a package lid attached to the package substrate and covering the semiconductor die. The package lid may include a top portion having a spatially varying thermal conductivity that is greater in a first region than in a second region. The first region may include a multi-layer structure including a metal/diamond composite material supported by a copper layer. The metal/diamond composite material may include a silver/diamond, copper/diamond, or aluminum/diamond material and may have a thermal conductivity that is within a range from 600 W/m·K to 900 W/m·K and a coefficient of thermal expansion that is in a second range from 5 ppm/° C. to 10 ppm/° C. The package lid may have an effective coefficient of thermal expansion that is in a range from 14.5 ppm/° C. to 17 ppm/° C.

公开(公告)号：US12074096B2

公开(公告)日：2024-08-27

申请号：US16793887

申请日：2020-02-18

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Pavone

IPC: H01L23/495 ,  H01L21/683 ,  H01L23/00 ,  H01L23/36 ,  H01L23/49 ,  H01L23/492 ,  H01L23/532

CPC classification number: H01L23/49517 ,  H01L23/49 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13007 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/013 ,  H01L2924/00014

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US20240282680A1

公开(公告)日：2024-08-22

申请号：US18440017

申请日：2024-02-13

Applicant: NEXPERIA B.V.

Inventor： Antonio B. Dimaano, JR. ,  Ricardo Yandoc ,  Homer Malveda ,  Marlon Fadullo

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49575 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2924/13091

Abstract: A leadframe for a semiconductor package is provided, including one or more mechanical standoffs for placing a die at a distance from the leadframe defined by a height of the standoffs and for enabling an adhesive layer between the leadframe and the die for bonding the die to the leadframe. The leadframe includes a substantially planar surface and the standoffs protrude from this surface. Surrounding perimeters, if present, of the leadframe are lower than the standoffs. The leadframe and the standoffs are a one-piece of conducting material and form a die paddle.

公开(公告)号：US12062622B2

公开(公告)日：2024-08-13

申请号：US17883568

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US20240258215A1

公开(公告)日：2024-08-01

申请号：US18162079

申请日：2023-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mei Jiao ,  Huo Yun Duan ,  Zi Qi Wang ,  Tiange Xie

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/181

Abstract: An example apparatus includes: a metal leadframe including a die pad in a central portion and leads spaced from the die pad. The leads include: an interior end spaced from the die pad and having a full thickness of the metal leadframe; a central portion connected to the interior end and extending away from the die pad having a partial thickness less than the full thickness; and an exterior end having the full thickness extending from the central portion. A semiconductor die is mounted to the die pad by die attach material. Wire bonds couple bond pads of the semiconductor die to the interior ends of the leads. Mold compound covers the semiconductor die, the die pad, the wire bonds, the interior ends of the leads, the central portion of the leads, and portions of the exterior ends of the leads to form a semiconductor device package.

公开(公告)号：US20240258186A1

公开(公告)日：2024-08-01

申请号：US18630486

申请日：2024-04-09

Applicant: Rohm Co., Ltd.

Inventor： Ryotaro KAKIZAKI ,  Koshun SAITO

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3121 ,  H01L23/49555 ,  H01L24/45 ,  H01L24/48 ,  H01L23/49513 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/46 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/46 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device includes a semiconductor element, a conductor, and a sealing resin. The conductor includes a die pad, a first terminal, and a second terminal. The sealing resin covers a portion of the conductor and the semiconductor element. The sealing resin includes first, second, third and fourth resin surfaces. The die pad includes a first-lead obverse surface with the semiconductor element mounted, and a first-lead reverse surface exposed from the second resin surface. The first terminal is bent in a first sense of z direction and exposed from the third resin surface. The second terminal is bent in the first sense of z direction and exposed from the fourth resin surface. The first resin surface includes a recessed region recessed in z direction toward the second resin surface. As viewed in z direction, the recessed region overlaps with an imaginary line connecting the first terminal and the second terminal.

公开(公告)号：US12051633B2

公开(公告)日：2024-07-30

申请号：US18317699

申请日：2023-05-15

Applicant: ROHM CO., LTD.

Inventor： Koshun Saito

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48175 ,  H01L2224/73265

Abstract: A semiconductor device includes a semiconductor element, first and second leads, and a sealing resin. The semiconductor element includes first and second electrodes. The first lead includes a mounting base having a main face to which the first electrode is bonded and a back face, and includes a first terminal connected to the first electrode. The second lead includes a second terminal connected to the second electrode. The sealing resin includes a main face and a back face opposite to each other, and includes an end face oriented in the protruding direction of the terminals. The back face of the mounting base is exposed from the back face of the resin. The sealing resin includes a groove formed in its back face and disposed between the back face of the mounting base and a boundary between the second terminal and the end face of the resin.