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公开(公告)号：US08959757B2
公开(公告)日：2015-02-24
申请号：US13339817
申请日：2011-12-29
Applicant: Thong Dang , Mohsen Haji-Rahim , Mark Charles Held
Inventor： Thong Dang , Mohsen Haji-Rahim , Mark Charles Held
IPC: H05K3/30
CPC classification number: H05K1/111 , H01L23/3135 , H01L23/3171 , H01L23/552 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/97 , H01L2224/24051 , H01L2224/24226 , H01L2224/245 , H01L2224/291 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/8201 , H01L2224/82031 , H01L2224/82101 , H01L2224/82136 , H01L2224/92244 , H01L2224/97 , H01L2924/1421 , H01L2924/1434 , H01L2924/1443 , H01L2924/1461 , H01L2924/15159 , H01L2924/15787 , H01L2924/19105 , H05K1/185 , H05K3/284 , H05K9/0022 , H05K2201/0715 , H05K2201/10439 , Y10T29/49016 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , H01L2224/82 , H01L2924/014 , H01L2924/00
Abstract: In one embodiment, a shielded electronic module is formed on a substrate. The substrate has a component area and one or more electronic components attached to the component area. One set of conductive pads may be attached to the component area and another set of conductive pads may be provided on the electronic component. The conductive pads on the component area are electrically coupled to the conductive pads of the electronic component by a conductive layer. A first insulating layer is provided over the component area and underneath the conductive layer that may insulate the electronic component and the substrate from the conductive layer. A second insulating layer is provided over the first insulating layer that covers at least the conductive layer. In this manner, the conductive layer is isolated from an electromagnetic shield formed over the component area.
Abstract translation: 在一个实施例中，屏蔽电子模块形成在基板上。 基板具有附接到部件区域的部件区域和一个或多个电子部件。 一组导电焊盘可以附接到部件区域，另外一组导电焊盘可以设置在电子部件上。 组件区域上的导电焊盘通过导电层电耦合到电子部件的导电焊盘。 第一绝缘层设置在导电层之上的部件区域和下方，可以使电子部件和衬底与导电层绝缘。 第二绝缘层设置在覆盖至少导电层的第一绝缘层上。 以这种方式，导电层与组件区域上形成的电磁屏蔽隔离。
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公开(公告)号：US20130154110A1
公开(公告)日：2013-06-20
申请号：US13328359
申请日：2011-12-16
Applicant: Arun Virupaksha Gowda
Inventor： Arun Virupaksha Gowda
CPC classification number: H01L24/24 , H01L23/3735 , H01L23/5389 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/50 , H01L2224/24137 , H01L2224/24195 , H01L2224/29101 , H01L2224/2919 , H01L2224/29339 , H01L2224/73267 , H01L2224/8201 , H01L2224/82101 , H01L2224/82102 , H01L2224/82103 , H01L2224/82104 , H01L2224/82106 , H01L2224/8384 , H01L2224/92244 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/00 , H01L2924/014 , H01L2924/00014
Abstract: A semiconductor device package having direct write interconnections and method of manufacturing thereof is disclosed. A device package is formed by providing a substrate structure, attaching at least one device to the substrate structure that each include a substrate and one or more connection pads formed on the substrate, depositing a dielectric layer over the at least one device and onto the substrate structure by way of a direct write application, the dielectric layer including vias formed therethrough, and forming an interconnect structure on the dielectric layer that is electrically coupled to the connection pads of the at least one device, the interconnect structure extending through the vias in the dielectric layer so as to be connected to the connection pads.
Abstract translation: 公开了一种具有直接写入互连的半导体器件封装及其制造方法。 通过提供衬底结构形成器件封装，将至少一个器件连接到衬底结构，每个器件包括衬底和形成在衬底上的一个或多个连接焊盘，在该至少一个器件上方沉积介电层并在衬底上 通过直接写入应用的结构，所述电介质层包括通过其形成的通孔，以及在所述电介质层上形成互连结构，所述互连结构电耦合到所述至少一个器件的连接焊盘，所述互连结构延伸穿过所述至少一个器件中的通孔 电介质层，以便连接到连接焊盘。
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Patent Agency Ranking
13.发明授权公开(公告)号：US09412728B2
公开(公告)日：2016-08-09
申请号：US14418842
申请日：2013-07-19
Inventor： Carlotta Guiducci , Yusuf Leblebici , Yuksel Temiz
CPC classification number: H01L25/50 , G03F7/2022 , G03F7/32 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3185 , H01L24/02 , H01L24/05 , H01L24/24 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2221/68381 , H01L2224/02313 , H01L2224/0239 , H01L2224/05166 , H01L2224/05624 , H01L2224/24011 , H01L2224/24051 , H01L2224/24146 , H01L2224/27002 , H01L2224/32145 , H01L2224/73267 , H01L2224/82002 , H01L2224/82005 , H01L2224/8201 , H01L2224/82101 , H01L2224/82106 , H01L2224/82143 , H01L2224/83143 , H01L2224/83203 , H01L2224/8385 , H01L2224/9202 , H01L2224/9205 , H01L2224/92244 , H01L2224/94 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/00014 , H01L2924/01013 , H01L2924/00013 , H01L2224/83 , H01L2224/82 , H01L2924/00
Abstract: A method for performing a post processing pattern on a diced chip having a footprint, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern.
Abstract translation: 一种用于在具有覆盖区的切割芯片上执行后处理图案的方法，包括以下步骤：提供支撑晶片; 将第一干膜光致抗蚀剂施加到所述支撑晶片; 将对应于切割的芯片的覆盖区的掩模定位在第一干膜光致抗蚀剂上; 将掩模和第一干膜光致抗蚀剂暴露于UV辐射; 取下面具; 光致抗蚀剂显影曝光的第一干膜光致抗蚀剂以获得与切割芯片相对应的空腔; 将切割的芯片定位在腔内; 将第二干膜光致抗蚀剂施加到第一膜光致抗蚀剂和切割的芯片上; 并且根据后处理图案曝光和显影施加到切割的芯片上的第二干膜光致抗蚀剂。
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14.发明授权公开(公告)号：US09209151B2
公开(公告)日：2015-12-08
申请号：US14037728
申请日：2013-09-26
Applicant: General Electric Company
Inventor： Shakti Singh Chauhan , Paul Alan McConnelee , Arun Virupaksha Gowda
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00 , H01L23/538 , H05K1/18 , H01L23/34 , H05K3/46 , H05K1/02 , H05K3/30
CPC classification number: H01L23/5389 , H01L23/34 , H01L23/367 , H01L23/3677 , H01L23/3736 , H01L23/42 , H01L23/433 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/53295 , H01L23/5384 , H01L23/5386 , H01L24/24 , H01L24/25 , H01L24/26 , H01L24/32 , H01L24/82 , H01L2224/04105 , H01L2224/12105 , H01L2224/2402 , H01L2224/24137 , H01L2224/24195 , H01L2224/24225 , H01L2224/2518 , H01L2224/2732 , H01L2224/27416 , H01L2224/291 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/8201 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/82101 , H01L2224/83005 , H01L2224/83132 , H01L2224/83192 , H01L2224/83855 , H01L2224/92144 , H01L2924/1203 , H01L2924/12042 , H01L2924/13091 , H01L2924/1433 , H01L2924/15747 , H01L2924/15787 , H01L2924/181 , H05K1/0266 , H05K1/185 , H05K3/305 , H05K3/4602 , H05K3/4605 , H05K3/4688 , H05K2201/0187 , H05K2203/0278 , H05K2203/063 , H05K2203/166 , H01L2924/014 , H01L2924/00
Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).
Abstract translation: 封装结构包括介电层，至少一个连接到电介质层的半导体器件，一个或多个施加到电介质层的电介质片和半导体器件，以将半导体器件嵌入其中，并且多个 形成在形成在电介质层和一个或多个电介质层中的至少一个中的半导体器件上的通孔。 封装结构还包括形成在通孔中的金属互连和在封装结构的一个或多个向外表面上以形成与半导体器件的电互连的金属互连。 电介质层由在层压过程中不流动的材料组成，并且所述一个或多个电介质片中的每一个由可固化材料构成，所述可固化材料构造成在层压过程中固化时熔化和流动，以便填充任何空气 半导体器件周围的间隙。
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公开(公告)号：US20150036306A1
公开(公告)日：2015-02-05
申请号：US14517002
申请日：2014-10-17
Applicant: RF Micro Devices, Inc.
Inventor： Thong Dang , Mohsen Haji-Rahim , Mark Charles Held
CPC classification number: H05K1/111 , H01L23/3135 , H01L23/3171 , H01L23/552 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/97 , H01L2224/24051 , H01L2224/24226 , H01L2224/245 , H01L2224/291 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/8201 , H01L2224/82031 , H01L2224/82101 , H01L2224/82136 , H01L2224/92244 , H01L2224/97 , H01L2924/1421 , H01L2924/1434 , H01L2924/1443 , H01L2924/1461 , H01L2924/15159 , H01L2924/15787 , H01L2924/19105 , H05K1/185 , H05K3/284 , H05K9/0022 , H05K2201/0715 , H05K2201/10439 , Y10T29/49016 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , H01L2224/82 , H01L2924/014 , H01L2924/00
Abstract: A shielded electronic module is formed on a substrate. The substrate has a component area and one or more electronic components attached to the component area. One set of conductive pads may be attached to the component area and another set of conductive pads may be provided on the electronic component. The conductive pads on the component area are electrically coupled to the conductive pads of the electronic component by a conductive layer. A first insulating layer is provided over the component area and underneath the conductive layer that may insulate the electronic component and the substrate from the conductive layer. A second insulating layer is provided over the first insulating layer that covers at least the conductive layer. In this manner, the conductive layer is isolated from an electromagnetic shield formed over the component area.
Abstract translation: 屏蔽电子模块形成在基板上。 基板具有附接到部件区域的部件区域和一个或多个电子部件。 一组导电焊盘可以附接到部件区域，另外一组导电焊盘可以设置在电子部件上。 组件区域上的导电焊盘通过导电层电耦合到电子部件的导电焊盘。 第一绝缘层设置在导电层之上的部件区域和下方，可以使电子部件和衬底与导电层绝缘。 第二绝缘层设置在覆盖至少导电层的第一绝缘层上。 以这种方式，导电层与组件区域上形成的电磁屏蔽隔离。
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公开(公告)号：US20140284795A1
公开(公告)日：2014-09-25
申请号：US14011930
申请日：2013-08-28
Applicant: SK hynix Inc.
Inventor： Sang Eun LEE , Chang Il KIM
IPC: H01L23/00
CPC classification number: H01L24/06 , H01L23/13 , H01L23/49883 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/83 , H01L24/92 , H01L2224/06155 , H01L2224/24105 , H01L2224/24226 , H01L2224/24227 , H01L2224/244 , H01L2224/245 , H01L2224/24997 , H01L2224/25175 , H01L2224/2612 , H01L2224/27436 , H01L2224/27442 , H01L2224/29015 , H01L2224/29036 , H01L2224/2919 , H01L2224/32225 , H01L2224/8201 , H01L2224/82097 , H01L2224/82105 , H01L2224/82138 , H01L2224/82143 , H01L2224/82385 , H01L2224/82815 , H01L2224/8291 , H01L2224/83138 , H01L2224/83192 , H01L2224/83855 , H01L2224/92144 , H01L2224/92244 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
Abstract: Various embodiments are directed to a semiconductor package and a method for manufacturing the same. A semiconductor package includes the following: a substrate having a plurality of connection pads; a semiconductor chip provided with a plurality of bonding pads on a first surface thereof and attached onto the substrate in a face-down position so that the bonding pads are positioned right above the corresponding connection pads; and thermoplastic conductive members introduced between the substrate and the semiconductor chip such that the bonding pad and the corresponding connection pad may be electrically connected.
Abstract translation: 各种实施例涉及半导体封装及其制造方法。 半导体封装包括以下：具有多个连接焊盘的衬底; 半导体芯片，其在其第一表面上设置有多个接合焊盘，并以面朝下的位置附接到所述基板上，使得所述接合焊盘位于相应的连接焊盘的正上方; 以及引入在基板和半导体芯片之间的热塑性导电构件，使得焊盘和相应的连接焊盘可以电连接。
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公开(公告)号：US20130170147A1
公开(公告)日：2013-07-04
申请号：US13339817
申请日：2011-12-29
Applicant: Thong Dang , Mohsen Haji-Rahim , Mark Charles Held
Inventor： Thong Dang , Mohsen Haji-Rahim , Mark Charles Held
CPC classification number: H05K1/111 , H01L23/3135 , H01L23/3171 , H01L23/552 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/97 , H01L2224/24051 , H01L2224/24226 , H01L2224/245 , H01L2224/291 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/8201 , H01L2224/82031 , H01L2224/82101 , H01L2224/82136 , H01L2224/92244 , H01L2224/97 , H01L2924/1421 , H01L2924/1434 , H01L2924/1443 , H01L2924/1461 , H01L2924/15159 , H01L2924/15787 , H01L2924/19105 , H05K1/185 , H05K3/284 , H05K9/0022 , H05K2201/0715 , H05K2201/10439 , Y10T29/49016 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , H01L2224/82 , H01L2924/014 , H01L2924/00
Abstract: In one embodiment, a shielded electronic module is formed on a substrate. The substrate has a component area and one or more electronic components attached to the component area. One set of conductive pads may be attached to the component area and another set of conductive pads may be provided on the electronic component. The conductive pads on the component area are electrically coupled to the conductive pads of the electronic component by a conductive layer. A first insulating layer is provided over the component area and underneath the conductive layer that may insulate the electronic component and the substrate from the conductive layer. A second insulating layer is provided over the first insulating layer that covers at least the conductive layer. In this manner, the conductive layer is isolated from an electromagnetic shield formed over the component area.
Abstract translation: 在一个实施例中，屏蔽电子模块形成在基板上。 基板具有附接到部件区域的部件区域和一个或多个电子部件。 一组导电焊盘可以附接到部件区域，另外一组导电焊盘可以设置在电子部件上。 组件区域上的导电焊盘通过导电层电耦合到电子部件的导电焊盘。 第一绝缘层设置在导电层之上的部件区域和下方，可以使电子部件和衬底与导电层绝缘。 第二绝缘层设置在覆盖至少导电层的第一绝缘层上。 以这种方式，导电层与组件区域上形成的电磁屏蔽隔离。
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