公开(公告)号：US20150070865A1

公开(公告)日：2015-03-12

申请号：US14025414

申请日：2013-09-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H05K1/11 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H05K1/0271 ,  H05K1/11 ,  H05K2201/09063 ,  H05K2201/10378 ,  H05K2201/10613 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.

Abstract translation: 本文公开了一种装置，其包括第一封装，第一封装具有设置在其上的多个连接器的第一侧和通过连接器安装在第一封装上的第二封装。 模制化合物设置在第一包装的第一侧上，并且在第一包装和第二包装之间。 多个应力消除结构（SRS）设置在模制化合物中，多个SRS在模制化合物中包括不含金属的空腔，并且与多个连接器中的每一个间隔开。

公开(公告)号：US11972190B1

公开(公告)日：2024-04-30

申请号：US18150509

申请日：2023-01-05

Applicant: Management Services Group, Inc.

Inventor： Thomas Scott Morgan ,  Martin Mayer ,  Steven Yates

IPC: H05K1/02 ,  G06F30/394 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  G06F115/12

CPC classification number: G06F30/394 ,  H05K1/0216 ,  H05K1/115 ,  H05K1/181 ,  H05K3/46 ,  G06F2115/12 ,  H05K2201/1006 ,  H05K2201/10159 ,  H05K2201/10613

Abstract: In some embodiments, an apparatus can include a printed circuit board (PCB) that has layers and includes a first portion and a second portion. The first portion can have a data port and a power port. A first layer is associated with data of the first portion of the PCB, and a second layer is associated with power of the first portion of the PCB. The second portion can have a data port and a power port. A third layer is associated with data of the second portion, and a fourth layer is associated with power of the second portion. The first portion or the second portion can have vias defining an electromagnetic interference (EMI) shield. The apparatus can include a power filter and a data filter that can, respectively, isolate power and data of the first portion from the second portion.

公开(公告)号：US09668344B2

公开(公告)日：2017-05-30

申请号：US14878891

申请日：2015-10-08

Applicant: SK hynix Inc.

Inventor： Won Duck Jung ,  Jong Ho Lee ,  Joo Hyun Kang ,  Chong Ho Cho ,  In Chul Hwang

IPC: H05K7/00 ,  H05K7/12 ,  H05K1/11 ,  H01L27/115 ,  H05K1/14 ,  H05K3/32

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/115 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81897 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/3511 ,  H05K1/145 ,  H05K3/32 ,  H05K3/325 ,  H05K2201/09209 ,  H05K2201/10159 ,  H05K2201/10287 ,  H05K2201/10613 ,  H05K2201/10757 ,  H05K2201/1078 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.

公开(公告)号：US20160316559A1

公开(公告)日：2016-10-27

申请号：US14878891

申请日：2015-10-08

Applicant: SK hynix Inc.

Inventor： Won Duck JUNG ,  Jong Ho LEE ,  Joo Hyun KANG ,  Chong Ho CHO ,  In Chul HWANG

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/115 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81897 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/3511 ,  H05K1/145 ,  H05K3/32 ,  H05K3/325 ,  H05K2201/09209 ,  H05K2201/10159 ,  H05K2201/10287 ,  H05K2201/10613 ,  H05K2201/10757 ,  H05K2201/1078 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.

Abstract translation: 半导体封装可以包括第一衬底，其包括设置在第一衬底的表面上的第一连接部分和包括设置在第二衬底的表面上的第二连接部分的第二衬底。 第二基板可以设置在第一基板上，第二连接部分面向第一连接部分。 可以提供第一连接环部分以包括连接到第一连接部分的端部。 可以提供第二连接环部分以包括连接到第二连接部分的一端和与第一连接环部分组合的另一端。

公开(公告)号：US20150083478A1

公开(公告)日：2015-03-26

申请号：US14484537

申请日：2014-09-12

Applicant: DAI-ICHI SEIKO CO., LTD.

Inventor： Takayoshi ENDO ,  Kenya ANDO

IPC: H05K1/18 ,  H01R43/02 ,  H05K3/30 ,  H01R4/02

CPC classification number: H05K1/181 ,  H01R4/02 ,  H01R12/707 ,  H01R12/724 ,  H01R43/0256 ,  H01R43/16 ,  H05K3/303 ,  H05K2201/10439 ,  H05K2201/10613 ,  Y10T29/49149 ,  Y10T29/49204

Abstract: The electric part to be soldered to a metal pad mounted on a printed circuit board, includes a first surface facing the metal pad, a second surface extending from the first surface in a direction away from the metal pad, and a third surface outwardly extending from the second surface, the second surface and the third surface defining a space in which solder is stored.

Abstract translation: 要焊接到安装在印刷电路板上的金属焊盘的电气部件包括面向金属焊盘的第一表面，从远离金属焊盘的方向从第一表面延伸的第二表面，以及从第一表面向外延伸的第三表面 第二表面，第二表面和第三表面限定存储焊料的空间。