公开(公告)号：US20240339390A1

公开(公告)日：2024-10-10

申请号：US18666369

申请日：2024-05-16

Applicant: Lodestar Licensing Group LLC

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/14179 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

公开(公告)号：US20240339380A1

公开(公告)日：2024-10-10

申请号：US18513108

申请日：2023-11-17

Applicant: TECH UNIVERSITY OF KOREA Industry Academic Cooperation Foundation

Inventor： Chang Kyu KIM

IPC: H01L23/48 ,  G01P5/12 ,  H01L23/13

CPC classification number: H01L23/481 ,  G01P5/12 ,  H01L23/13

Abstract: A semiconductor-type wind speed sensor is provided. The semiconductor-type wind speed sensor includes a substrate including a through hole, a pair of electrodes formed on the substrate, and a metal wire configured to electrically connect the pair of electrodes.

公开(公告)号：US20240297108A1

公开(公告)日：2024-09-05

申请号：US18278501

申请日：2022-02-24

Applicant: KYOCERA CORPORATION

Inventor： Kanae HORIUCHI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49176

Abstract: An electronic element mounting board includes a bottom portion including a mounting surface, a side portion positioned surrounding the mounting surface of the bottom portion, and a conductor forming a part of the side portion. The side portion includes a first surface located on a side of the mounting surface and a recessed portion surface recessed from the first surface. The conductor includes an outer surface located on the recessed portion surface. The electronic element mounting board further includes a coating film covering the outer surface. The optical reflectance of the coating film is lower than the optical reflectance of the conductor.

公开(公告)号：US12068324B2

公开(公告)日：2024-08-20

申请号：US17358790

申请日：2021-06-25

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L27/10 ,  H01G4/228 ,  H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L49/02 ,  H01L23/50 ,  H01L25/10

CPC classification number: H01L27/101 ,  H01G4/228 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/642 ,  H01L24/14 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

公开(公告)号：US12057357B2

公开(公告)日：2024-08-06

申请号：US17212417

申请日：2021-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong Hwan Koh ,  Jongwan Kim ,  Juhyeon Oh ,  Yongkwan Lee

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52 ,  H01L23/00

CPC classification number: H01L23/13 ,  H01L21/4803 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/73265

Abstract: A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.

公开(公告)号：US12040261B2

公开(公告)日：2024-07-16

申请号：US17707801

申请日：2022-03-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Syu-Tang Liu ,  Tsung-Tang Tsai ,  Huang-Hsien Chang ,  Ching-Ju Chen

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H05K1/11

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238

Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.

公开(公告)号：US12009270B2

公开(公告)日：2024-06-11

申请号：US17607901

申请日：2019-11-14

Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY ,  GUANGDONG LUCKYSTAR ELECTRONIC TECHNOLOGY CO., LTD ,  SHENZHEN GOOD-MACHINE AUTOMATIC EQUIPMENT CO., LTD

Inventor： Zongtao Li ,  Yong Tang ,  Hong Wang ,  Shudong Yu ,  Kejian Wu ,  Guanwei Liang ,  Xinrui Ding

IPC: H01L23/13 ,  H01L23/15 ,  H01L33/62

CPC classification number: H01L23/13 ,  H01L23/15 ,  H01L33/62

Abstract: The present invention discloses a welding method of a demetallized ceramic substrate having a surface capillary microgroove structure. The demetallized ceramic substrate includes a ceramic substrate main body and surface capillary microstructures. The surface capillary microstructures are arranged on two lateral sides of the ceramic substrate main body and the surface capillary microstructures specifically are capillary microgrooves. The welding method includes the following steps: fixing a chip to an upper surface of the demetallized ceramic substrate having the surface capillary microgroove structure, fixing the ceramic substrate with the chip to a printed circuit board having a bonding pad, and placing melted solder on the bonding pad, and driving the solder to ascend to an electrode of the chip from the bonding pad in a lower layer by means of a capillary force, thereby realizing an electrical connection between the chip and the printed circuit board.

公开(公告)号：US20240186251A1

公开(公告)日：2024-06-06

申请号：US18075360

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Minglu LIU ,  YANG WU ,  Yuting WANG ,  Lawrence ROSS ,  Mine KAYA ,  Gang DUAN ,  Edvin CETEGEN ,  Alexander AGUINAGA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/13 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2924/351

Abstract: Embodiments disclosed herein include package architectures. In an embodiment, the package architecture comprises a package substrate, a first bridge in the package substrate, where the first bridge includes conductive routing, and a second bridge in the package substrate. In an embodiment, the package architecture further comprises a third bridge in the package substrate, where the second bridge and the third bridge are positioned symmetrically about the first bridge.

公开(公告)号：US20240178206A1

公开(公告)日：2024-05-30

申请号：US17994355

申请日：2022-11-27

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Sang Hyeon LEE ,  Kyoung Yeon LEE ,  Jae Beom SHIM ,  Yi Seul HAN ,  Ji Yeon RYU ,  Woo Jun KIM

IPC: H01L25/16 ,  G02B6/42 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L25/167 ,  G02B6/4257 ,  G02B6/426 ,  G02B6/4262 ,  G02B6/428 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1616 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/182

Abstract: In one example, an electronic device includes a first substrate and a second substrate. The first substrate includes a substrate first side, a substrate second side, and a first conductive structure. An inner electronic component is coupled to the first conductive structure proximate to the substrate second side. An outer electronic component is coupled to the first conductive structure proximate to the substrate first side. The outer electronic component includes a body and a groove in the body configured to couple with an external interconnect. Inner interconnects couple the first substrate to the second substrate. The first substrate, the second substrate, the inner electronic component, and the outer electronic component are in a stacked configuration. The inner electronic component is interposed between the first substrate and the second substrate. Other examples and related methods are also disclosed herein.

公开(公告)号：US20240178162A1

公开(公告)日：2024-05-30

申请号：US18060125

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2223/6616

Abstract: An integrated circuit (IC) package substrate including a glass core having a cavity filter structure, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include a core made of glass, and the core including a first core portion having a first surface and a trench and a ridge in the first surface, the trench and the ridge lined with a conductive material; and a second core portion having a second surface, the second surface lined with the conductive material, wherein the first surface of the first core portion is physically coupled to the second surface of the second core portion forming a cavity filter structure.