公开(公告)号：US20060032310A1

公开(公告)日：2006-02-16

申请号：US11201268

申请日：2005-08-10

Applicant: Angelo Merassi ,  Bruno Murari ,  Sarah Zerbini

Inventor： Angelo Merassi ,  Bruno Murari ,  Sarah Zerbini

IPC: G01P15/08 ,  H01L23/48

CPC classification number: G01P15/125 ,  B81B7/0048 ,  B81B2201/0235 ,  G01P1/006 ,  G01P2015/082

Abstract: In a micro-electromechanical structure, a rotor has a centroidal axis and includes a suspended structure which carries mobile electrodes. A stator carries fixed electrodes facing the mobile electrodes. The suspended structure is connected to a rotor-anchoring region via elastic elements. The stator includes at least one stator element, which carries a plurality of fixed electrodes and is fixed to a stator-anchoring region. One of the rotor-anchoring regions and stator-anchoring regions extends along the centroidal axis and at least another of the rotor-anchoring regions and stator-anchoring regions extends in the proximity of the centroidal axis.

Abstract translation: 在微机电结构中，转子具有重心轴线，并且包括携带移动电极的悬挂结构。 定子承载面向移动电极的固定电极。 悬挂结构通过弹性元件连接到转子 - 锚定区域。 定子包括至少一个定子元件，该定子元件承载多个固定电极并固定到定子 - 锚定区域。 转子锚定区域和定子 - 锚定区域之一沿着重心轴线延伸，并且至少另一个转子 - 锚定区域和定子 - 锚定区域在重心轴线附近延伸。

公开(公告)号：US20060023999A1

公开(公告)日：2006-02-02

申请号：US11172384

申请日：2005-06-29

Applicant: Guido Chiaretti

Inventor： Guido Chiaretti

IPC: G02B6/34

CPC classification number: H01S5/02248 ,  G02B6/02176 ,  G02B6/022 ,  G02B6/421 ,  H01S3/1053 ,  H01S5/02216 ,  H01S5/02284 ,  H01S5/02415 ,  H01S5/02438 ,  H01S5/02484 ,  H01S5/146

Abstract: A method of producing an optical device including a Bragg grating formed in an optical waveguide, the method comprising: providing a support substrate; positioning the optical waveguide with respect to an optical source so as to achieve a desired optical coupling of optical power emitted by the optical source into the optical waveguide; attaching the waveguide to the support substrate in correspondence of a first location along the waveguide, said first location being at one side of the Bragg grating; attaching the waveguide to the support substrate in a correspondence of a second location along the waveguide, said second location being at an opposite side of the Bragg grating, so as to freeze a first stress condition in the Bragg grating.

Abstract translation: 一种制造包括形成在光波导中的布拉格光栅的光学器件的方法，所述方法包括：提供支撑衬底; 将光波导相对于光源定位，以便实现由光源发射到光波导中的光功率的期望的光耦合; 将波导附着到沿着波导的第一位置的支撑衬底上，所述第一位置在布拉格光栅的一侧; 沿着波导的第二位置对应地将波导附接到支撑基板，所述第二位置在布拉格光栅的相反侧，从而冻结布拉格光栅中的第一应力状态。

公开(公告)号：US20060018067A1

公开(公告)日：2006-01-26

申请号：US11185905

申请日：2005-07-20

Applicant: Daniele Vimercati ,  Osama Khouri ,  Sara Fiorina

Inventor： Daniele Vimercati ,  Osama Khouri ,  Sara Fiorina

IPC: H02H3/00

CPC classification number: G11C16/30 ,  G11C5/063 ,  G11C5/14

Abstract: A method of distributing an electric quantity through an electronic circuit for local exploitation by at least one circuit block of the electronic circuit that includes providing in the electronic circuit first and second conductive lines, the first conductive line distributing a first electric potential and the second conductive line carrying a second electric potential that is a dedicated reference electric potential for the first electric potential, the first and second electric potentials corresponding to the distributed electric quantity, and locally exploiting the distributed electric quantity by at least one circuit block of the electronic circuit, by locally reconstructing the distributed electric quantity from the first and second electric potentials without perturbing them, particularly without either sinking or injecting any significant current from or into the first and second conductive lines.

公开(公告)号：US20060015792A1

公开(公告)日：2006-01-19

申请号：US11175960

申请日：2005-07-05

Applicant: Andrea Vitali ,  Stefano Olivieri

Inventor： Andrea Vitali ,  Stefano Olivieri

IPC: H03M13/00

CPC classification number: H04N19/67 ,  H04N19/132 ,  H04N19/176 ,  H04N19/18 ,  H04N19/37 ,  H04N19/39 ,  H04N19/48 ,  H04N19/59 ,  H04N19/61

Abstract: A system for encoding digital signals for transmission over a channel by allocating redundant channel encoding bits, includes at least one encoder configured for: subjecting the digital signals to multiple description coding to produce therefrom multiple description encoded signals, and allocating at least part of the redundant channel encoding bits to the multiple description encoded signals.

公开(公告)号：US20050264907A1

公开(公告)日：2005-12-01

申请号：US11137946

申请日：2005-05-26

Applicant: Angelo Dati ,  Augusto Rossi ,  Davide Giovenzana

Inventor： Angelo Dati ,  Augusto Rossi ,  Davide Giovenzana

IPC: G11B27/30 ,  G11B5/09

CPC classification number: G11B27/3027 ,  G11B2220/20

Abstract: A method for storing user data on a hard disk drive system comprises distributing user data across a plurality of independent data sectors, with each data sector including a first header having a first preamble field and a first sync mark field, and a second header having a second preamble field and a second sync mark field. The method performs a first timing recovery phase for recovering signal amplitude by acquiring phase and frequency lock from at least one of the preamble fields, and performs a subsequent frame synchronous detection phase by acquiring a corresponding sync mark field.

Abstract translation: 一种用于在硬盘驱动器系统上存储用户数据的方法包括在多个独立数据扇区之间分配用户数据，每个数据扇区包括具有第一前同步码字段和第一同步标记字段的第一标题，以及具有 第二前同步码字段和第二同步标记字段。 该方法通过从前导字段中的至少一个获取相位和频率锁定来执行用于恢复信号幅度的第一定时恢复阶段，并且通过获取对应的同步标记字段来执行后续的帧同步检测阶段。

公开(公告)号：US20050258998A1

公开(公告)日：2005-11-24

申请号：US11113954

申请日：2005-04-25

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno

IPC: G11C27/02 ,  H03H19/00 ,  H03K5/24 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46

CPC classification number: G11C27/026 ,  G11C27/024 ,  H03H19/004 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/468

Abstract: A switched capacitance circuit including: a switched capacitance section, capable of receiving as input a signal and carrying out a sampling of said signal, the section comprising at least one group of capacitors each of which has a terminal connected to a common node; at least an operational stage including at least an input terminal connected to said common node, the operational stage providing a current to said common node for charging said group of capacitors during a sampling time interval of said signal. The circuit further includes an auxiliary circuit connected to said common node and capable of being activated/deactivated by an enabling signal for injecting a further current into said common node and increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.

Abstract translation: 一种开关电容电路，包括：开关电容部分，其能够接收信号并执行所述信号的采样，所述部分包括至少一组电容器，每个电容器的一组电容器具有连接到公共节点的端子; 至少包括连接到所述公共节点的输入端的操作级，所述操作级在所述信号的采样时间间隔期间向所述公共节点提供电流，以对所述电容器组进行充电。 该电路还包括连接到所述公共节点的辅助电路，并且能够通过用于将另外的电流注入到所述公共节点中的使能信号来激活/去激活，并且在至少等于一个等待时间间隔的至少一个时间间隔期间增加提供给所述公共节点的电流 所述采样间隔的分数。

公开(公告)号：US20050253644A1

公开(公告)日：2005-11-17

申请号：US11113818

申请日：2005-04-25

Applicant: Luca Crippa ,  Miriam Sangalli ,  Salvatrice Scommegna ,  Rino Micheloni

Inventor： Luca Crippa ,  Miriam Sangalli ,  Salvatrice Scommegna ,  Rino Micheloni

IPC: G05F3/30 ,  G11C5/14 ,  G11C29/02 ,  H03H11/26

CPC classification number: G11C5/147 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block. Further, a change in the second IC functional parameter in response to the corresponding change in the trimming configuration of the second functional block is proportional to the change in the first IC functional parameter consequent to the change in the trimming configuration of the first functional block.

Abstract translation: 用于修整集成电路IC-（100）的功能参数的修整结构包括第一（115a）和至少一个第二功能块（115b，...，115n），第一（Vr1，...，115n） ）和至少一个第二IC功能参数（Vrg，b，...，Vrg，n）分别相关联。 修剪结构包括包括在第一和至少一个第二功能块中的相应可调节电路结构（205a，210a，...，205n，210n），以及修剪配置存储（110），用于存储用于 可调节电路结构。 第一功能块的修整配置的变化导致第二功能块的修整配置的相应变化。 此外，响应于第二功能块的修整配置的相应变化，第二IC功能参数的变化与第一功能块的修整配置的改变所引起的第一IC功能参数的变化成比例。

公开(公告)号：US20050151207A1

公开(公告)日：2005-07-14

申请号：US11050196

申请日：2005-02-03

Applicant: Alessandro Moscatelli ,  Giuseppe Croce

Inventor： Alessandro Moscatelli ,  Giuseppe Croce

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

Abstract translation: 集成在半导体材料晶片中的金属氧化物半导体晶体管包括位于晶片表面上并包括栅极氧化物层的栅极结构。 栅极氧化物层包括具有第一厚度的第一部分和具有不同于第一厚度的第二厚度的第二部分。

公开(公告)号：US20050112905A1

公开(公告)日：2005-05-26

申请号：US10971774

申请日：2004-10-22

Applicant: Emilio Camerlenghi ,  Alfonso Maurelli ,  Daniela Peschiaroli ,  Paola Zabberoni

Inventor： Emilio Camerlenghi ,  Alfonso Maurelli ,  Daniela Peschiaroli ,  Paola Zabberoni

IPC: H01L21/8234 ,  H01L21/8247 ,  H01L23/31 ,  H01L27/105 ,  H01L21/44 ,  B32B7/12 ,  B32B15/04 ,  H01L21/31 ,  H01L21/469 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L27/11526 ,  H01L21/823468 ,  H01L23/3192 ,  H01L27/105 ,  H01L27/11536 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.

Abstract translation: 用于密封形成在半导体衬底上的电子器件的方法包括在半导体衬底的用于限定电子器件的第一部分上形成至少一个第一导电层，以及在半导体衬底的第二部分上形成第二导电层，用于还限定电子器件 。 第一区域形成在用于限定电子器件的至少一个第一导电层中，并且在整个半导体衬底上形成第一密封层以密封第一区域。 第二区域形成在用于限定电子器件的第二导电层中，并且在整个半导体衬底上形成第二密封层以密封第二区域。

公开(公告)号：US20050063236A1

公开(公告)日：2005-03-24

申请号：US10913788

申请日：2004-08-06

Applicant: Mauro Pagliato ,  Massimo Montanaro ,  Paolo Rolandi

Inventor： Mauro Pagliato ,  Massimo Montanaro ,  Paolo Rolandi

IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C11/34

CPC classification number: G11C11/5642 ,  G11C7/06 ,  G11C7/062 ,  G11C7/067 ,  G11C16/28

Abstract: A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, equalizing means, and a comparator. The equalizing means selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing means are such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.

Abstract translation: 提供了一种读出放大器，其包括接收待检测的输入电流的测量分支，接收参考电流的参考分支，均衡装置和比较器。 均衡装置选择性地将测量分支的测量节点与参考分支的参考节点进行均衡，并且比较器将测量分支的测量节点处的电压与参考分支的参考节点处的电压进行比较。 均衡装置使得当激活时，具有参考节点的测量节点的均衡是虚拟的并且基本上不涉及测量节点和参考分支的参考节点之间的电流。 读出放大器特别适用于读取半导体存储器的存储单元。 还提供了用于感测输入电流的方法。