公开(公告)号：US20170133265A1

公开(公告)日：2017-05-11

申请号：US15417848

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/285 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0895 ,  H01L29/66795 ,  H01L29/7851

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

公开(公告)号：US09646969B2

公开(公告)日：2017-05-09

申请号：US15208121

申请日：2016-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20170125551A1

公开(公告)日：2017-05-04

申请号：US14925630

申请日：2015-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/66795 ,  H01L21/225 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US09634004B2

公开(公告)日：2017-04-25

申请号：US15181992

申请日：2016-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L23/31 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices include a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.

公开(公告)号：US20170069627A1

公开(公告)日：2017-03-09

申请号：US15181992

申请日：2016-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L29/417 ,  H01L21/8234 ,  H01L23/31 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semicondcutor devices include a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.

Abstract translation: 半切割器装置包括一对翅片上的钝化层。 阻挡层延伸穿过钝化层并在一对翅片之间并且电隔离散热片。 电触头通过钝化层形成到散热片。 电触点直接接触屏障的侧壁。

公开(公告)号：US09548306B2

公开(公告)日：2017-01-17

申请号：US15144924

申请日：2016-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Andres Bryant ,  Tenko Yamashita

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/45

Abstract: In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.

Abstract translation: 在形成半导体结构的方法中，介电层的不同部分在处理期间在不同的阶段被蚀刻，以形成用于第一FET（例如，NFET）的第一栅极侧壁间隔件和用于第二FET的第二栅极侧壁间隔物 例如PFET），使得第一和第二栅极侧壁间隔物是对称的。 在第一栅极侧壁间隔物形成之后立即形成用于第一FET的升高的源极/漏极区，并且在第二栅极侧壁间隔物形成之后立即形成用于第二FET的升高的源极/漏极区。 由于两个FET的栅极侧壁间隔物是对称的，所以两个FET的源极/漏极结也将是对称的。 另外，由于形成在第一FET的升高的源极/漏极区上而不是第二FET的蚀刻停止层，不同的FET的升高的源极/漏极区上的不同的金属硅化物。

公开(公告)号：US09536982B1

公开(公告)日：2017-01-03

申请号：US14930895

申请日：2015-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L29/51 ,  H01L21/31 ,  H01L29/78 ,  H01L29/423 ,  H01L21/283 ,  H01L21/768 ,  H01L23/522 ,  H01L21/764 ,  H01L21/8238

CPC classification number: H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Abstract translation: 一种在半导体器件的沟道区上包括栅极结构的半导体器件。 源极和漏极区域可以存在于沟道区域的相对侧上。 半导体器件还可以包括存在于栅极结构的侧壁上的复合栅极侧壁间隔物。 复合栅极侧壁间隔物可以包括其中封装有气隙的第一组合物部分和完全固体并存在于第一组合物部分顶部的第二组合物部分。

公开(公告)号：US09437501B1

公开(公告)日：2016-09-06

申请号：US14861326

申请日：2015-09-22

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092 ,  H01L27/12 ,  H01L21/74

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

Abstract translation: 制造纳米线器件的方法包括在衬底上设置第一纳米线堆叠，第一纳米线堆叠包括第一和第二半导体材料的交替层，第一半导体材料与衬底接触，第二半导体材料是暴露表面; 在所述衬底上设置第二纳米线堆叠，所述第二纳米线堆叠包括所述第一和第二半导体材料的交替层，所述第一半导体材料与所述衬底接触，所述第二半导体材料为暴露表面; 沿着第一纳米线堆叠上的第一栅极区域的侧壁形成第一栅极间隔物，并且沿着第二纳米线堆叠件上的第二栅极区域的侧壁形成第二栅极间隔物; 氧化所述第一栅极间隔物内的所述第一纳米线堆叠的一部分; 以及从所述第一纳米线堆叠和所述第二纳米线堆叠中去除所述第一半导体材料。

公开(公告)号：US09373697B2

公开(公告)日：2016-06-21

申请号：US14509392

申请日：2014-10-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sanjay C. Mehta ,  Shom S. Ponoth ,  Muthumanickam Sankarapandian ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785

Abstract: A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.

公开(公告)号：US09349863B2

公开(公告)日：2016-05-24

申请号：US13961522

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Krishna Iyengar ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

Abstract translation: 在形成栅极结构和栅极间隔物之后，蚀刻半导体鳍片下面的绝缘体层的部分，以从源极区域和漏极区域下面物理地暴露下面的半导体材料层的半导体表面。 扩展源极区域和延伸漏极区域中的每一个包括锚定的单晶半导体材料部分，其与下面的半导体材料层的单晶半导体结构外延对准，并向半导体鳍片横向施加应力。 因为每个锚定的单晶半导体材料部分与下面的半导体材料层进行外延对准，所以鳍状场效应晶体管的沟道沿着半导体鳍片的长度方向被有效地应力。