公开(公告)号：US3886415A

公开(公告)日：1975-05-27

申请号：US30956472

申请日：1972-11-24

Applicant: ITEK CORP

Inventor： GENTHE JAMES E

IPC: G03C1/705 ,  G03G17/02 ,  H01G4/10 ,  H01G13/00 ,  H01L49/02 ,  H05K1/00 ,  H05K1/16 ,  H05K3/18 ,  H01G3/06

CPC classification number: H05K3/185 ,  G03C1/705 ,  G03G17/02 ,  H01G4/10 ,  H01G13/00 ,  H01L49/02 ,  H05K1/0393 ,  H05K1/162 ,  H05K3/1266 ,  H05K2201/0209 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0517

Abstract: An electrical component production method wherein an electrically conductive image electrode is exposed and photographically developed on the surface of a substrate supported photoconductive layer.

Abstract translation: 一种电子部件制造方法，其中导电图像电极在基板支撑的光电导层的表面上曝光和照相显影。

公开(公告)号：US3217209A

公开(公告)日：1965-11-09

申请号：US2864260

申请日：1960-05-12

Applicant: XEROX CORP

Inventor： KINSELLA JOHN J ,  SCHWERTZ FREDERICK A

IPC: H01G2/00 ,  H05K1/16 ,  H05K3/06 ,  H05K3/38

CPC classification number: H01G2/00 ,  H05K1/16 ,  H05K1/162 ,  H05K1/167 ,  H05K3/06 ,  H05K3/061 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09763

公开(公告)号：US20180286595A1

公开(公告)日：2018-10-04

申请号：US15994807

申请日：2018-05-31

Applicant: Micron Technology, Inc.

Inventor： Fred D. Fishburn

IPC: H01G4/38 ,  H01G4/30

CPC classification number: H01G4/385 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30 ,  H01G4/40 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H01L28/00 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16265 ,  H01L2924/19041 ,  H01L2924/19104 ,  H05K1/162 ,  H05K2201/09763 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

公开(公告)号：US09905928B2

公开(公告)日：2018-02-27

申请号：US14268082

申请日：2014-05-02

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: H01Q15/02 ,  H01Q9/04 ,  B82Y30/00 ,  H01C7/00 ,  H01C17/00 ,  H01C17/065 ,  H01G4/10 ,  H01G4/33 ,  H01Q1/22 ,  H01Q1/38 ,  H01Q15/00 ,  H01L23/64 ,  H01L23/498 ,  H05K1/02 ,  H05K1/09 ,  H05K1/16 ,  H05K3/20

CPC classification number: H01Q9/0414 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q15/0086 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T428/12493

Abstract: An electrical component provides a ceramic element located on or in a dielectric substrate between and in contact with a pair of electrical conductors, wherein the ceramic element includes one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.5 mol % throughout the ceramic element. A method of fabricating an electrical component, provides or forming a ceramic element between and in contact with a pair of electrical conductors on a substrate including depositing a mixture of metalorganic precursors and causing simultaneous decomposition of the metal oxide precursors to form the ceramic element including one or more metal oxides.

公开(公告)号：US20170142836A1

公开(公告)日：2017-05-18

申请号：US14943299

申请日：2015-11-17

Applicant: Martin Brokner Christiansen ,  Leonard George Chorosinski ,  H. Craig Heffner ,  Stanley Katsuyoshi Wakamiya ,  Keith R. Kirkwood

Inventor： Martin Brokner Christiansen ,  Leonard George Chorosinski ,  H. Craig Heffner ,  Stanley Katsuyoshi Wakamiya ,  Keith R. Kirkwood

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/46 ,  H05K3/30 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/181 ,  H05K1/0203 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/303 ,  H05K3/46 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/09063 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09763

Abstract: A circuit card assembly includes a substrate having longitudinally spaced first and second substrate end edges and transversely spaced top and bottom substrate surfaces. The top and/or bottom substrate surface has first, second, and third substrate regions. The first substrate region is directly laterally adjacent the first substrate side edge. The third substrate region is directly laterally adjacent the second substrate side edge. The second substrate region is located between the first and third substrate regions. At least one circuit trace is located on the selected substrate surface. The portion of the circuit trace in the first substrate region is made of only a first material. The portion of the circuit trace in the third substrate region is made of only a second material. The portion of the circuit trace in the second substrate region is made of both the first and second materials.

公开(公告)号：US20160330839A1

公开(公告)日：2016-11-10

申请号：US15111305

申请日：2015-02-20

Applicant: MITSUI MINING & SMELTING CO., LTD.

Inventor： Fujio KUWAKO ,  Toshifumi MATSUSHIMA ,  Toshihiro HOSOI

IPC: H05K1/16 ,  H05K3/42 ,  H05K1/09 ,  B32B15/20 ,  H05K3/00 ,  H05K3/02 ,  H05K1/11 ,  B32B15/04 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/162 ,  B32B15/00 ,  B32B15/04 ,  B32B15/20 ,  B32B2307/51 ,  B32B2457/00 ,  B32B2457/08 ,  B32B2457/16 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/022 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0154 ,  H05K2201/09763

Abstract: Object is to provide a material for forming of the capacitor layer which generates no crack in drilling on the dielectric layer of the capacitor in manufacturing of a highly multilayered printed wiring board embedded a capacitor circuit. To achieve the object, copper clad laminate for forming of an embedded capacitor layer of a multilayered printed wiring board including an embedded capacitor circuit having a layer structure of copper layer/dielectric layer of the capacitor/copper layer in an inner layer characterized in that the Young's modulus Er of the resin film constituting the dielectric layer of the capacitor along the thickness direction is less than 6.1 GPa is employed.

Abstract translation: 目的是提供一种用于形成电容器层的材料，其在嵌入电容器电路的高度多层印刷线路板的制造中在电容器的电介质层上不产生裂纹。 为了实现该目的，为了形成具有在内层中具有电容器/铜层的铜层/电介质层的层结构的嵌入式电容电路的多层印刷布线板的嵌入式电容器层的覆铜层压板，其特征在于， 构成电容器的厚度方向的电介质层的树脂膜的杨氏模量Er小于6.1GPa。

公开(公告)号：US20150357112A1

公开(公告)日：2015-12-10

申请号：US14560935

申请日：2014-12-04

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

CPC classification number: H01F27/2804 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01F3/00 ,  H01F5/003 ,  H01F27/24 ,  H01F27/29 ,  H01F27/40 ,  H01F41/041 ,  H01F2027/2809 ,  H01G4/10 ,  H01G4/33 ,  H01L23/64 ,  H01L28/10 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T29/49021

Abstract: A power management module, provides an inductor including one or more electrical conductors disposed around a ferromagnetic ceramic element including one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.50 mol % throughout the ceramic element.

Abstract translation: 电源管理模块提供一种电感器，其包括设置在铁磁性陶瓷元件周围的一个或多个电导体，所述铁磁陶瓷元件包括在整个陶瓷元件中具有小于或等于1.50摩尔％的金属氧化物组成均匀性波动的一种或多种金属氧化物。

公开(公告)号：US08730647B2

公开(公告)日：2014-05-20

申请号：US12203340

申请日：2008-09-03

Applicant: Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

Inventor： Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

IPC: H05K1/16 ,  H01G4/228 ,  H01L23/522

CPC classification number: H05K1/162 ,  H05K3/0044 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09845 ,  H05K2203/025 ,  H05K2203/1476

Abstract: A printed wiring board includes a capacitor including a dielectric body having a first surface and a second surface, a first electrode provided on the first surface of the dielectric body, and a second electrode provided on the second surface of the dielectric body. The first electrode has an area facing and being smaller than the first surface of the dielectric body, and the second electrode has an area facing and being larger than the second surface of the dielectric body.

Abstract translation: 印刷布线板包括电容器，其包括具有第一表面和第二表面的电介质体，设置在电介质体的第一表面上的第一电极和设置在电介质体的第二表面上的第二电极。 第一电极具有面向并小于电介质体的第一表面的面积，并且第二电极具有面向并大于电介质体的第二表面的面积。

公开(公告)号：US08652920B2

公开(公告)日：2014-02-18

申请号：US13409424

申请日：2012-03-01

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethla Melody ,  Antony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethla Melody ,  Antony P. Chacko ,  Gregory J. Dunn

IPC: H01L27/108 ,  H01G4/005

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract translation: 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

公开(公告)号：US08289725B2

公开(公告)日：2012-10-16

申请号：US12851795

申请日：2010-08-06

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K7/00

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.

Abstract translation: 提供具有嵌入式电容器的封装基板。 封装衬底包括芯电路板，至少一个电介质层，至少一个嵌入式电容器和至少一个金属层。 核心电路板具有至少一个布线层，并且核心电路板具有连接到布线层的至少一个导电通孔。 至少一个电介质层覆盖布线层，电介质层具有至少一个导电通孔。 至少一个嵌入式电容器嵌入电介质层。 至少一个金属层覆盖电介质层并连接到嵌入式电容器，其中金属层通过导电通孔连接到布线层。