公开(公告)号：US10056468B2

公开(公告)日：2018-08-21

申请号：US15258333

申请日：2016-09-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth Balaji Samavedan ,  Manfred Eller ,  Min-hwa Chi ,  Hui Zang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US09960077B1

公开(公告)日：2018-05-01

申请号：US15679848

申请日：2017-08-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Josef Watts ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L27/088 ,  G03F7/20 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/76264 ,  G03F7/70633 ,  H01L21/02381 ,  H01L21/02496 ,  H01L21/28141 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: Methods of forming a self-aligned CT pillar with the same CD width as the device fins to enable PC isolation and the resulting devices are provided. Embodiments include forming a plurality of fins over a substrate; forming an oxide layer over the substrate and between each fin; removing a portion of a central fin among the plurality, a trench formed in the oxide layer; forming a CT pillar in the trench; recessing the oxide layer below an upper surface of the plurality of fins; forming a gate over the plurality of fins and CT pillar; planarizing the gate down to the CT pillar; and forming a cap layer over the gate and CT pillar.

公开(公告)号：US09911825B2

公开(公告)日：2018-03-06

申请号：US15443522

申请日：2017-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3213

CPC classification number: G01P15/00 ,  G01C22/006 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one fin; forming at least one sacrificial gate with at least one barrier layer; forming a first set of spacers adjacent to the at least one sacrificial gate; forming at least one second set of spacers adjacent to the first set of spacers; and etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09905661B2

公开(公告)日：2018-02-27

申请号：US15185801

申请日：2016-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L29/76 ,  H01L29/417 ,  H01L21/768 ,  H01L23/535 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/41725 ,  H01L21/28 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/088 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.

公开(公告)号：US09876089B2

公开(公告)日：2018-01-23

申请号：US15183390

申请日：2016-06-15

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jin Cho ,  MiaoMiao Wang ,  Hui Zang

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/28 ,  H01L21/324 ,  H01L29/49

CPC classification number: H01L29/513 ,  H01L21/28026 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

公开(公告)号：US09865603B2

公开(公告)日：2018-01-09

申请号：US14662734

申请日：2015-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L27/11 ,  H01L21/82 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

公开(公告)号：US09831317B1

公开(公告)日：2017-11-28

申请号：US15447639

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L29/41741 ,  H01L21/28556 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

公开(公告)号：US09748392B1

公开(公告)日：2017-08-29

申请号：US15053867

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanzhen Wang ,  Jidong Huang ,  Hui Zang

IPC: H01L21/283 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/285 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/28008 ,  H01L21/2855 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: An angled gas cluster ion beam is used for each sidewall and top of a fin (two applications) to form work-function metal layer(s) only on the sidewalls and top of each fin.

公开(公告)号：US20170243782A1

公开(公告)日：2017-08-24

申请号：US15047137

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Hui Zang

IPC: H01L21/762 ,  H01L21/308 ,  H01L27/12 ,  H01L21/311 ,  H01L29/08 ,  H01L29/06 ,  H01L21/84 ,  H01L21/3213

CPC classification number: H01L21/76283 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847

Abstract: One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region.

公开(公告)号：US09691787B2

公开(公告)日：2017-06-27

申请号：US14878332

申请日：2015-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L27/1207 ,  H01L21/8234 ,  H01L21/84

Abstract: Bulk semiconductor devices are co-fabricated on a bulk semiconductor substrate with SOI devices. The SOI initially covers the entire substrate and is then removed from the bulk device region. The bulk device region has a thicker dielectric on the substrate than the SOI region. The regions are separated by isolation material, and may or may not be co-planar.