公开(公告)号：US10381357B2

公开(公告)日：2019-08-13

申请号：US16043653

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20190013319A1

公开(公告)日：2019-01-10

申请号：US15642148

申请日：2017-07-05

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Kamal M. Karda

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879

Abstract: Some embodiments include a memory cell having a transistor with a channel region between a first source/drain region and a second source/drain region. A controlled-conductivity region is adjacent the first source/drain region. The controlled-conductivity region has a low-conductivity mode and a high-conductivity mode. The high-conductivity mode has a conductivity at least 106 greater than a conductivity of the low-conductivity mode. The channel region includes a first material having a first bandgap, and the controlled-conductivity region includes a second material having a second bandgap which is greater than the first bandgap. A charge-storage device is electrically coupled to the first source/drain region through the controlled-conductivity region. A bitline is electrically coupled to the second source/drain region.

公开(公告)号：US09577092B2

公开(公告)日：2017-02-21

申请号：US14517261

申请日：2014-10-17

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

IPC: H01L29/78 ,  G11C11/40 ,  H01L27/02 ,  H01L27/105 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

公开(公告)号：US09564576B2

公开(公告)日：2017-02-07

申请号：US14941088

申请日：2015-11-13

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  F. Daniel Gealy ,  D. V. Nirmal Ramaswamy ,  Chandra V. Mouli

IPC: G11C11/22 ,  H01L43/02 ,  H01L43/12 ,  G11C11/56 ,  H01L27/115 ,  H01L49/02

CPC classification number: G11C11/5657 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H01L27/11507 ,  H01L28/40 ,  H01L43/02 ,  H01L43/12

Abstract: Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

Abstract translation: 提供了多位铁电存储器件及其形成方法。 形成多位铁电存储器件的一个示例性方法可以包括在通孔的第一侧上形成第一铁电材料，去除材料以暴露通孔的第二面，并在第二侧上形成第二铁电材料 与通孔的第一侧相比具有不同的厚度。

公开(公告)号：US09559194B2

公开(公告)日：2017-01-31

申请号：US15003679

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/267 ,  H01L21/02 ,  H01L27/115 ,  H01L29/12 ,  H01L29/786

CPC classification number: H01L45/1206 ,  H01L21/02532 ,  H01L21/02568 ,  H01L23/535 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/12 ,  H01L29/267 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/66977 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L43/02 ,  H01L43/10 ,  H01L45/142 ,  H01L45/143

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract translation: 一些实施例包括具有漏极区域和源极区域的晶体管。 导电栅极位于源区和漏区之间。 第一通道材料位于栅极和源极区域之间。 第一通道材料通过一种或多种绝缘材料与栅极间隔开。 第二通道材料位于第一通道材料和源极区之间，并直接接触源区。 第一和第二通道材料是过渡金属硫属化物。 源区和漏区中的一个是孔储存区，另一个是电子储存区。 隧道介电材料可以在第一和第二通道材料之间。

公开(公告)号：US09559118B2

公开(公告)日：2017-01-31

申请号：US15095211

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/24 ,  H01L29/78 ,  G11C11/22

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

Abstract translation: 垂直铁电场效应晶体管结构包括隔离芯。 过渡金属二硫属元素材料环绕隔离芯并具有1个单层至7个单层的侧壁厚度。 铁电栅极电介质材料围绕过渡金属二硫属元素材料。 导电栅极材料围绕铁电栅极电介质材料。 过渡金属二硫属元素材料在导电栅极材料的高度向内和向外向外延伸。 导电接触件直接抵靠过渡金属二硫属化物材料的侧向外侧壁，其是导电栅极材料的顶部向内，或b）导电栅极材料的向外侧。 公开了另外的实施例。

公开(公告)号：US09391206B2

公开(公告)日：2016-07-12

申请号：US14992966

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

公开(公告)号：US20160155829A1

公开(公告)日：2016-06-02

申请号：US15003679

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L45/1206 ,  H01L21/02532 ,  H01L21/02568 ,  H01L23/535 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/12 ,  H01L29/267 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/66977 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L43/02 ,  H01L43/10 ,  H01L45/142 ,  H01L45/143

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract translation: 一些实施例包括具有漏极区域和源极区域的晶体管。 导电栅极位于源区和漏区之间。 第一通道材料位于栅极和源极区域之间。 第一通道材料通过一种或多种绝缘材料与栅极间隔开。 第二通道材料位于第一通道材料和源极区之间，并直接接触源区。 第一和第二通道材料是过渡金属硫族化物。 源区和漏区中的一个是孔储存区，另一个是电子储存区。 隧道介电材料可以在第一和第二通道材料之间。

公开(公告)号：US20160072044A1

公开(公告)日：2016-03-10

申请号：US14941088

申请日：2015-11-13

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  F. Daniel Gealy ,  D.V. Nirmal Ramaswamy ,  Chandra V. Mouli

IPC: H01L43/02 ,  H01L43/12

CPC classification number: G11C11/5657 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H01L27/11507 ,  H01L28/40 ,  H01L43/02 ,  H01L43/12

Abstract: Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

公开(公告)号：US09276134B2

公开(公告)日：2016-03-01

申请号：US14519021

申请日：2014-10-20

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/11 ,  H01L29/792 ,  H01L29/66 ,  H01L27/115 ,  H01L29/06 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L27/2454 ,  H01L21/02568 ,  H01L27/11582 ,  H01L27/2463 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/7926 ,  H01L45/065 ,  H01L45/141 ,  H01L45/16

Abstract: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

Abstract translation: 在一些实施例中，晶体管包括具有底部源极/漏极区域，第一绝缘材料，导电栅极，第二绝缘材料和顶部源极/漏极区域的堆叠。 该堆叠具有沿着底部源极/漏极区域具有底部的垂直侧壁，沿着导电栅极的中间部分和沿着顶部源极/漏极区域的顶部部分。 第三绝缘材料沿着垂直侧壁的中间部分。 沟道区域材料沿着第三绝缘材料。 通道区域材料直接抵靠垂直侧壁的顶部和底部。 沟道区域材料的厚度在大于约至小于或等于的范围内; 和/或具有1个单层至7个单层的厚度。