公开(公告)号：US06740222B2

公开(公告)日：2004-05-25

申请号：US09876522

申请日：2001-06-07

Applicant: Charles Cohn

Inventor： Charles Cohn

IPC: C25D502

CPC classification number: H05K3/243 ,  H05K3/062 ,  H05K3/108 ,  H05K3/242 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2203/0571 ,  H05K2203/1572 ,  H05K2203/1581

Abstract: The present invention provides a method of plating an electrical contact on an integrated circuit (IC) substrate manufactured from a rigid double-sided or multi-layered printed wiring board core with dielectric layers on both sides of the core. The method may include forming electrically connected plating layers on first and second opposing sides of a substrate and electroplating a contact layer over each of the plating layers using the plating layers. The method further includes removing a portion of the plating layers from the first and second opposing sides while leaving the plating layers under the contact layer.

Abstract translation: 本发明提供了一种在由芯的两侧具有电介质层的刚性双面或多层印刷线路板芯制造的集成电路（IC）基板上电镀电接触的方法。 该方法可以包括在基板的第一和第二相对侧上形成电连接的镀层，并且使用镀层在每个镀层上电镀接触层。 该方法还包括从第一和第二相对侧去除一部分镀层，同时将镀层留在接触层下方。

公开(公告)号：US06731189B2

公开(公告)日：2004-05-04

申请号：US10185853

申请日：2002-06-27

Applicant: Angelo Puzella ,  Joseph M. Crowder ,  Patricia S. Dupuis ,  Michael C. Fallica

Inventor： Angelo Puzella ,  Joseph M. Crowder ,  Patricia S. Dupuis ,  Michael C. Fallica

IPC: H01L21768

CPC classification number: H01P3/085 ,  H01P3/088 ,  H05K1/0237 ,  H05K3/321 ,  H05K3/462 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10234 ,  H05K2203/061

Abstract: A multi-layer stripline assembly interconnection includes a first stripline sub-assembly having a first surface and a first plurality of vias disposed in the first surface adapted to receive a plurality of solid metal balls. The interconnection further includes a second stripline sub-assembly having a second plurality of vias disposed in the first surface of the second sub-assembly adapted to be aligned with the first plurality of vias. Reflowed solder is wetted to the second plurality of vias and to the corresponding plurality of solid metal balls.

Abstract translation: 多层带状线组合互连包括具有第一表面的第一带状线子组件和设置在第一表面中的适于容纳多个固体金属球的第一多个通孔。 互连还包括第二带状线子组件，其具有设置在第二子组件的第一表面中的适于与第一多个通孔对准的第二多个通孔。 回流焊料被润湿到第二多个通孔和对应的多个固体金属球。

公开(公告)号：US20040041243A1

公开(公告)日：2004-03-04

申请号：US10432005

申请日：2003-09-22

Inventor： Tsuyoshi Ogawa

IPC: H01L023/495

CPC classification number: H01L23/49894 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/498 ,  H01L23/49822 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/16 ,  H05K1/162 ,  H05K1/167 ,  H05K3/062 ,  H05K3/067 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/09509 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K2203/1453 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a thin film circuit board device having passive elements in wiring layers. The thin film circuit board device includes a base board (2) and a circuit part (3) including insulating layers (11) and (16) and pattern wiring (14) and (17) formed on a build-up forming surface (2a). On the first insulating layer (11), a receiving electrode part (21) is formed and the passive elements electrically connected to the receiving electrode part (21) are formed. In the circuit part (3), a substrate titanium film and a substrate film are laminated so as to cover the receiving electrode part (21) and the passive elements respectively. The substrate film and the substrate titanium film in areas in which a metallic film is not formed are etched through the metallic film serving as the first pattern wiring (14) formed on the substrate film as a mask. Thus, a substrate layer (23) and a substrate titanium layer (22) are formed. Consequently, the substrate titanium film serving as the substrate titanium layer (22) prevents the corrosion of the receiving electrode part and the respective passive elements due to etching liquid to form the passive elements with high performance.

Abstract translation: 本发明涉及一种在布线层中具有无源元件的薄膜电路板器件。 薄膜电路板装置包括基板（2）和包括绝缘层（11）和（16）的电路部分（3）和形成在堆积形成表面（2a）上的图案布线（14）和（17） ）。 在第一绝缘层（11）上，形成接收电极部（21），并且形成与接收电极部（21）电连接的无源元件。 在电路部分（3）中，层叠基板钛膜和基板膜以覆盖接收电极部分（21）和无源元件。 通过作为形成在基板膜上的第一图案布线（14）的金属膜作为掩模，蚀刻在未形成金属膜的区域中的基板膜和基板钛膜。 因此，形成基板层（23）和基板钛层（22）。 因此，用作基板钛层（22）的基板钛膜防止由于蚀刻液体而导致的接收电极部分和各个无源元件的腐蚀，从而形成具有高性能的无源元件。

公开(公告)号：US20040040744A1

公开(公告)日：2004-03-04

申请号：US10101211

申请日：2002-03-20

Inventor： Aneta D. Wyrzykowska ,  Luigi G. Difilippo ,  Herman Kwong

IPC: H05K007/08

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49155

Abstract: A technique for reducing the number of layers in a multilayer circuit board is disclosed. The multilayer circuit board has a plurality of electrically conductive signal layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer circuit board. In one embodiment, the technique is realized by a method for reducing the number of layers in a multilayer circuit board, the multilayer circuit board having a plurality of electrically conductive signal layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer circuit board. The method comprises the steps of: forming a plurality of electrically conductive vias in the multilayer circuit board extending from the surface of the multilayer circuit board to at least one of the plurality of electrically conductive signal layers; arranging the surface such that a first set of two power/ground pins corresponds to first via and a second set of two power/ground pins corresponds to a second via positioned adjacent the first via, thereby creating a channel; and routing a first plurality of electrical signals through the channel on the first of the plurality of electrically conductive signal layers.

Abstract translation: 公开了一种用于减少多层电路板中的层数的技术。 多层电路板具有多个导电信号层，用于将电信号传送到安装在多层电路板的表面上的至少一个电子部件和/或从安装在多层电路板的表面上的至少一个电子部件。 在一个实施例中，该技术通过一种用于减少多层电路板中的层数的方法实现，该多层电路板具有多个用于将电信号路由至至少一个安装在 多层电路板的表面。 该方法包括以下步骤：在多层电路板中形成从多层电路板的表面延伸到多个导电信号层中的至少一个的多个导电通孔; 布置表面使得第一组两个电源/接地引脚对应于第一通孔，并且第二组两个电源/接地引脚对应于邻近第一通孔定位的第二通孔，从而产生通道; 以及通过所述多个导电信号层中的所述第一导电信号层上的所述沟道路由第一多个电信号。

公开(公告)号：US06681483B2

公开(公告)日：2004-01-27

申请号：US10125221

申请日：2002-04-18

Applicant: E. James Crescenzi, Jr. ,  Anwar A. Mohammed

Inventor： E. James Crescenzi, Jr. ,  Anwar A. Mohammed

IPC: H01K310

CPC classification number: H05K3/44 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0047 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09554 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/171 ,  H05K2203/175 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit architecture includes a relatively thick, stiffening base of thermally and electrically conductive material, and a laminate of conductive layers including a printed circuit structure, interleaved with dielectric layers, disposed atop the base. The patterned conductive layers contain an integrated circuit structure that is configured to provide RF signaling, microstrip shielding, and digital and analog control signal leads, and DC power. Low inductance electrical connectivity among the conductive layers and also between conductive layers and the base is provided by a plurality of conductive bores. Selected bores are counter-drilled at the RF signaling layer and filled with insulating plugs, which prevent shorting of the RF signal trace layer to ground, during solder reflow connection of leads of circuit components to the RF signaling layer.

Abstract translation: 印刷电路架构包括相对厚的加热和导电材料的加强基底，以及布置在基底顶部的包括与电介质层交织的印刷电路结构的导电层的层压体。 图案化导电层包含被配置为提供RF信号，微带屏蔽以及数字和模拟控制信号引线以及DC电力的集成电路结构。 导电层之间以及导电层和基底之间的低电感电连接由多个导电孔提供。 选择的孔在RF信号层反相钻孔，并填充有绝缘插头，以防止将RF信号迹线层短路到地，将电路部件的引线与RF信号层焊接回流连接。

公开(公告)号：US06678144B2

公开(公告)日：2004-01-13

申请号：US10083788

申请日：2002-02-27

Applicant: Mitsutoshi Higashi ,  Koji Omori ,  Takashi Mochizuki

Inventor： Mitsutoshi Higashi ,  Koji Omori ,  Takashi Mochizuki

IPC: H01G4228

CPC classification number: H01G9/028 ,  H01G9/042 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0329 ,  H05K2201/09509 ,  H05K2203/0315 ,  H01L2924/00

Abstract: A capacitor is formed between a lower wiring layer and an upper wiring layer in an interior of a circuit board. The capacitor is formed of a lower metallic layer which is of at least one valve metal selected from the group consisting of aluminum, tantalum, niobium, tungsten, vanadium, bismuth, titanium, zirconium and hafnium, a dielectric layer which is of an oxide of the valve metal which may be the same as or different from the valve metal of the lower metallic layer, an intermediate layer which is of a solid electrolyte, and an upper metallic layer which is of an electrode metal, laminated in this order.

Abstract translation: 在电路板的内部的下布线层和上布线层之间形成电容器。 所述电容器由选自铝，钽，铌，钨，钒，铋，钛，锆和铪中的至少一种阀金属的下金属层形成，介电层为氧化物 可以与下金属层的阀金属相同或不同的阀金属，固体电解质的中间层和电极金属的上金属层依次层叠。

公开(公告)号：US20040003941A1

公开(公告)日：2004-01-08

申请号：US10326079

申请日：2002-12-23

Inventor： Guy A. Duxbury ,  Herman Kwong ,  Aneta Wyrzykowska ,  Luigi G. Difilippo

IPC: H05K007/06

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A technique for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as an interconnect array for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device having a plurality of electrically conductive signal path layers. In such a case, the interconnect array comprises a plurality of electrically conductive contacts grouped into a plurality of arrangements of electrically conductive contacts, wherein each of the plurality of arrangements of electrically conductive contacts are separated from other adjacent ones of the plurality of arrangements of electrically conductive contacts by a channel that is correspondingly formed in the multilayer signal routing device such that an increased number of electrical signals may be routed therein on the plurality of electrically conductive signal path layers.

Abstract translation: 公开了一种用于电连接电子部件和多层信号路由装置之间的电信号的技术。 在一个特定的示例性实施例中，该技术可以被实现为用于电连接电子部件和具有多个导电信号路径层的多层信号路由装置之间的电信号的互连阵列。 在这种情况下，互连阵列包括分组成多个导电触头布置的多个导电触头，其中导电触头的多个布置中的每一个与多个电气布置的其它相邻布置分离 通过相应地形成在多层信号路由设备中的信道的导电接触，使得可以在多个导电信号路径层上路由增加数量的电信号。

公开(公告)号：US06670102B2

公开(公告)日：2003-12-30

申请号：US09978124

申请日：2001-10-15

Applicant: Ryoichi Watanabe

Inventor： Ryoichi Watanabe

IPC: G03F726

CPC classification number: H05K3/421 ,  H05K3/0094 ,  H05K3/064 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2203/135

Abstract: A method for manufacturing a circuit board having a conductive via comprises the steps of providing a substrate having a first surface and a first conductive layer on at least one region of the first surface, forming an insulating layer on the first conductive layer, forming an opening in the insulating layer, so that the opening extending to the first conductive layer, forming a second conductive layer inside the opening and at least on the insulating layer near the opening, applying a positive photoresist on the second conductive layer, exposing the positive photoresist, developing the exposed positive photoresist, and removing the positive photoresist on the second conductive layer, except a portion of the second conductive layer that is inside the opening, etching the second conductive layer, to expose a surface of the second conductive layer, removing the positive photoresist from inside the opening, and forming a third conductive layer inside the opening.

公开(公告)号：US20030221314A1

公开(公告)日：2003-12-04

申请号：US10358219

申请日：2003-02-05

Applicant: NITTO DENKO CORPORATION

Inventor： Toshiki Naito ,  Yoshifumi Shinogi ,  Daisuke Uenda

IPC: H05K003/10

CPC classification number: H05K1/0265 ,  H05K3/064 ,  H05K3/108 ,  H05K3/388 ,  H05K3/421 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0574 ,  H05K2203/0577 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/24917

Abstract: A method for manufacturing a double-sided circuit board from a board material having a first electric conductor layer and a first electrically insulating layer, including the steps of: making conduction holes in the board material so as to penetrate only the first electrically insulating layer or both the first electrically insulating layer and the first electric conductor layer; forming an electrically conductive thin-film layer on a surface of the first electrically insulating layer and wall surfaces of the conduction holes; forming a second electrically insulating layer on the electrically conductive thin-film layer; forming a first electric conductor wiring by electroplating on predetermined portions of the electrically conductive thin-film layer; covering the first electric conductor wiring with a chemical-resistant film; forming a second electric conductor wiring by chemically dissolving a predetermined portion of another surface of the first electric conductor layer; and removing the second electrically insulating layer and the film.

Abstract translation: 一种从具有第一导电体层和第一电绝缘层的基板材料制造双面电路板的方法，包括以下步骤：在基板材料中形成导电孔，以仅穿透第一电绝缘层或 第一电绝缘层和第一导电体层; 在第一电绝缘层的表面和导电孔的壁表面上形成导电薄膜层; 在所述导电薄膜层上形成第二电绝缘层; 通过电镀在导电薄膜层的预定部分上形成第一导电体布线; 用耐化学性膜覆盖第一导电线; 通过化学溶解所述第一导电体层的另一个表面的预定部分来形成第二导电体布线; 以及去除所述第二电绝缘层和所述膜。

公开(公告)号：US06631838B2

公开(公告)日：2003-10-14

申请号：US09832122

申请日：2001-04-11

Applicant: Nam-Jin Kim ,  Young-Cheol Ahn ,  Won-Jae Kim

Inventor： Nam-Jin Kim ,  Young-Cheol Ahn ,  Won-Jae Kim

IPC: B23K3524

CPC classification number: H05K3/0094 ,  H05K3/1216 ,  H05K3/28 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2203/0759 ,  H05K2203/085 ,  H05K2203/1476

Abstract: A method for fabricating a printed circuit board includes the steps of: fabricating a printed circuit board having at least one collapsed portion; depositing a first solder resist in the collapsed portion; exposing the first solder resist-coated printed circuit board at a pressure lower than atmospheric pressure for a predetermined time; coating a second solder resist on the entire surface of the printed circuit board; and drying and hardening the first and the second solder resists. With this method, when a solder resist is coated, since an air space does not remain in a blind via hole, the reliability of the attachment between a printed circuit board and the solder resist layer is increased.

Abstract translation: 制造印刷电路板的方法包括以下步骤：制造具有至少一个折叠部分的印刷电路板; 在折叠部分中沉积第一阻焊剂; 将第一耐焊锡涂布印刷电路板在低于大气压的压力下暴露预定时间; 在印刷电路板的整个表面上涂覆第二阻焊剂; 并干燥和硬化第一和第二阻焊剂。 利用这种方法，当涂覆阻焊剂时，由于空气空间不保留在盲孔中，所以印刷电路板和阻焊层之间的连接的可靠性增加。