公开(公告)号：US09640493B2

公开(公告)日：2017-05-02

申请号：US14829292

申请日：2015-08-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L21/768 ,  H01L27/02 ,  G06F17/50

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

公开(公告)号：US20170116439A1

公开(公告)日：2017-04-27

申请号：US15137789

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Jimmy Fort ,  Clement Champeix ,  Jean-Max Dutertre ,  Nicolas Borrel

IPC: G06F21/86 ,  H03K5/153 ,  H03K5/24 ,  H01L23/00

CPC classification number: G06F21/86 ,  G09C1/00 ,  H01L23/576 ,  H03K5/153 ,  H03K5/24 ,  H04L9/004 ,  H04L2209/12

Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.

公开(公告)号：US20170097653A1

公开(公告)日：2017-04-06

申请号：US15150713

申请日：2016-05-10

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Nicolas DEMANGE ,  Jimmy FORT ,  Thierry SOUDE

IPC: G05F3/26 ,  H03B29/00 ,  H01L23/00

CPC classification number: G05F3/262 ,  G06F21/755 ,  G06K19/0723 ,  H01L23/576 ,  H03B29/00

Abstract: A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.

公开(公告)号：US20170092357A1

公开(公告)日：2017-03-30

申请号：US15054015

申请日：2016-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C5/144 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C29/12005

Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.

公开(公告)号：US09583193B2

公开(公告)日：2017-02-28

申请号：US14864354

申请日：2015-09-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G11C16/12 ,  H01L27/115

CPC classification number: G11C16/0483 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11534 ,  H01L29/7881

Abstract: Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the at least one memory cell with a programming voltage split between a positive voltage and a negative voltage.

Abstract translation: 集成的非易失性存储器件包括具有浮置栅极晶体管的EEPROM类型的集成存储器单元和串联连接在源极线和位线之间的选择晶体管，以及用于存储器单元的编程电路。 选择晶体管连接在浮栅晶体管和源极线之间。 编程电路被配置为用在正电压和负电压之间分压的编程电压对所述至少一个存储器单元进行编程。

公开(公告)号：US09577116B2

公开(公告)日：2017-02-21

申请号：US14963684

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

Abstract translation: 本发明涉及一种齐纳二极管，其包括具有第一导电类型的阴极区，形成在具有第二导电类型的半导体衬底的表面上。 齐纳二极管包括形成在阴极区下面的具有第二导电类型的阳极区域。 一个或多个沟槽隔离将阴极和阳极区域与衬底的其余部分隔离。 第一导电区域被配置为当经受足够的电压时，产生垂直于阴极和阳极区域之间的界面的第一电场。 第二导电区域被配置为当经受足够的电压时，产生平行于阴极和阳极区域之间的界面的第二电场。

公开(公告)号：US09559297B2

公开(公告)日：2017-01-31

申请号：US15214054

申请日：2016-07-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Julien Delalleau

IPC: H01L43/12 ,  H01L27/24 ,  H01L27/115 ,  H01L27/22 ,  H01L29/423 ,  H01L29/78 ,  H01L45/00 ,  H01L43/02 ,  H01L43/08 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L43/12 ,  H01L21/26513 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11507 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/42356 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of making a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.

Abstract translation: 本公开涉及一种在半导体衬底上制造存储器的方法，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，其具有连接到 所述选择线，连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成在所述衬底中的沟槽中产生的嵌入垂直栅极，以及 与沟槽的第一面相对的沟道区，位于耦合到可变阻抗元件的衬底表面上的第一深掺杂区和第二掺杂区之间。

公开(公告)号：US20170012104A1

公开(公告)日：2017-01-12

申请号：US15068732

申请日：2016-03-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/423 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L21/02236 ,  H01L21/28167 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

Abstract translation: 在基板中形成集成的MOS晶体管。 晶体管包括掩埋在衬底的沟槽中的栅极区域。 栅极区域被覆盖沟槽内壁的电介质区域围绕。 源极区域和漏极区域位于沟槽的相对侧上的衬底中。 电介质区域包括至少部分地位于栅极区域的上部与源极和漏极区域之间的上部电介质区域。 所述电介质区域还包括下部电介质区域，所述下部电介质区域比所述上部电介质区域厚，并且位于所述栅极区域的下部和所述衬底之间。

公开(公告)号：US20170011804A1

公开(公告)日：2017-01-12

申请号：US15276462

申请日：2016-09-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/26 ,  H01L27/115 ,  G11C16/08 ,  H01L21/28 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/14 ,  H01L21/0276 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储单元，包括：第一晶体管，包括控制栅极，浮置栅极和漏极区域;第二晶体管，包括控制栅极，浮置栅极和漏极区域， 其中第一和第二晶体管的浮置栅极电耦合，并且第二晶体管包括电耦合到其漏极区域并且通过隧道电介质层与其浮动栅极相对延伸的导电区域。

公开(公告)号：US09543018B2

公开(公告)日：2017-01-10

申请号：US14964196

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C8/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C8/12 ,  G11C8/08

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.

Abstract translation: 本公开涉及包括具有至少两行存储器单元的存储器阵列的存储器，耦合到第一行存储器单元的控制线的第一驱动器和耦合到第二行存储器单元的控制线的第二驱动器 记忆细胞 第一驱动器在第一阱中制造，第二驱动器在与第一阱电绝缘的第二阱中制造，并且两行存储器单元在与第一阱和第二阱良好地电绝缘的存储器阵列中产生。