公开(公告)号：US08496159B2

公开(公告)日：2013-07-30

申请号：US13154412

申请日：2011-06-06

Applicant: Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

Inventor： Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

IPC: B23K3/00 ,  B23K3/06

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: Solder bumps of uniform height are provided on a substrate through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned layer of photoresist. Solder is injected over the pillars or BLM, filling the channels. The solder, which does not contain flux, is allowed to solidify. It forms a plurality of solder structures (bumps) of equal heights. Solder injection and solidification are preferably carried out in a nitrogen environment or a forming gas environment. Molten solder can be injected in channels formed in round wafers without spillage using a carrier assembly that accommodates such wafers and a fill head.

Abstract translation: 通过使用注射成型的焊料在基板上设置均匀高度的焊料凸块。 在图案化的光致抗蚀剂层的通道内的I / O焊盘上形成铜柱或极限极限冶金。 焊料注入柱子或BLM，填充通道。 允许不含焊剂的焊料固化。 它形成相同高度的多个焊料结构（凸块）。 焊接注入和固化优选在氮气环境或形成气体环境中进行。 可以使用容纳这种晶片和填充头的载体组件将熔融焊料注入到以圆形晶片形成的通道中而不会溢出。

公开(公告)号：US08381966B2

公开(公告)日：2013-02-26

申请号：US13036086

申请日：2011-02-28

Applicant: Rajneesh Kumar ,  Jae-Woong Nah ,  Eric D. Perfecto

Inventor： Rajneesh Kumar ,  Jae-Woong Nah ,  Eric D. Perfecto

IPC: B23K31/02 ,  H01L21/44

CPC classification number: B23K1/0016

Abstract: A first substrate mounted to a bonder head and a second substrate mounted to a base plate are held at different elevated temperatures at the time of bonding that provide a substantially matched thermal expansion between the second substrate and the first substrate relative to room temperature. Further, the temperature of the solder material portions and the second substrate is raised at least up to the melting temperature after contact. The distance between the first substrate and the second substrate can be modulated to enhance the integrity of solder joints. Once the distance is at an optimum, the bonder head is detached, and the bonded structure is allowed to cool to form a bonded flip chip structure. Alternately, the bonder head can control the cooling rate of solder joints by being attached to the chip during cooling step.

Abstract translation: 安装到接合头的第一衬底和安装到基板的第二衬底在接合时被保持在不同的升高的温度，从而相对于室温在第二衬底和第一衬底之间提供基本匹配的热膨胀。 此外，焊接材料部分和第二基板的温度至少升高到接触后的熔融温度。 第一基板和第二基板之间的距离可被调制以增强焊点的完整性。 一旦该距离处于最佳状态，就将分离头拆下，并使粘结结构冷却以形成结合的倒装芯片结构。 或者，焊接头可以在冷却步骤期间通过附接到芯片来控制焊点的冷却速度。

公开(公告)号：US20120305631A1

公开(公告)日：2012-12-06

申请号：US13525855

申请日：2012-06-18

Applicant: Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

Inventor： Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

IPC: B23K31/02 ,  B23K1/20

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: Solder bumps of uniform height are provided on a substrate through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned layer of photoresist. Solder is injected over the pillars or BLM, filling the channels. The solder, which does not contain flux, is allowed to solidify. It forms a plurality of solder structures (bumps) of equal heights. Solder injection and solidification are preferably carried out in a nitrogen environment or a forming gas environment. Molten solder can be injected in channels formed in round wafers without spillage using a carrier assembly that accommodates such wafers and a fill head.

Abstract translation: 通过使用注射成型的焊料在基板上设置均匀高度的焊料凸块。 在图案化的光致抗蚀剂层的通道内的I / O焊盘上形成铜柱或极限极限冶金。 焊料注入柱子或BLM，填充通道。 允许不含焊剂的焊料固化。 它形成相同高度的多个焊料结构（凸块）。 焊接注入和固化优选在氮气环境或形成气体环境中进行。 可以使用容纳这种晶片和填充头的载体组件将熔融焊料注入到以圆形晶片形成的通道中而不会溢出。

公开(公告)号：US06361627B1

公开(公告)日：2002-03-26

申请号：US09569483

申请日：2000-05-11

Applicant: Patrick W. DeHaven ,  Charles C. Goldsmith ,  Jeffery L. Hurd ,  Suryanarayana Kaja ,  Michele S. Legere ,  Eric D. Perfecto

Inventor： Patrick W. DeHaven ,  Charles C. Goldsmith ,  Jeffery L. Hurd ,  Suryanarayana Kaja ,  Michele S. Legere ,  Eric D. Perfecto

IPC: C12D604

CPC classification number: C25D5/50 ,  H05K1/09 ,  H05K3/22 ,  H05K2203/0723 ,  H05K2203/1105 ,  Y10T428/12431 ,  Y10T428/12882 ,  Y10T428/12903

Abstract: A process for controlling grain growth in the microstructure of thin metal films (e.g., copper or gold) deposited onto a substrate. In one embodiment, the metal film is deposited onto the substrate to form a film having a fine-grained microstructure. The film is heated in a temperature range of 70-100°C. for at least five minutes, wherein the fine-grained microstructure is converted into a stable large-grained microstructure. In another embodiment, the plated film is stored, after the step of depositing, at a temperature not greater than −20° C., wherein the fine-grained microstructure is stabilized without grain growth for the entire storage period.

Abstract translation: 控制沉积在基底上的薄金属薄膜（例如铜或金）的微结构中的晶粒生长的方法。 在一个实施方案中，将金属膜沉积到基底上以形成具有细晶粒微结构的膜。 该膜在70-100℃的温度范围内加热。 至少5分钟，其中细晶粒微结构转化为稳定的大粒度微结构。 在另一个实施方案中，在沉积步骤之后，在不大于-20℃的温度下储存镀膜，其中在整个储存期间细晶粒微结构稳定而没有晶粒生长。

公开(公告)号：US06235412B1

公开(公告)日：2001-05-22

申请号：US09544075

申请日：2000-04-06

Applicant: Tien-Jen Cheng ,  Ajay P. Giri ,  Ashwani K. Malhotra ,  John R. Pennacchia ,  Eric D. Perfecto ,  Roy Yu

Inventor： Tien-Jen Cheng ,  Ajay P. Giri ,  Ashwani K. Malhotra ,  John R. Pennacchia ,  Eric D. Perfecto ,  Roy Yu

IPC: B32B1500

CPC classification number: H01L21/4853 ,  C25D7/123 ,  H01L24/16 ,  H05K3/4007 ,  Y10S428/929 ,  Y10S428/935 ,  Y10T428/12847 ,  Y10T428/12875 ,  Y10T428/12889

Abstract: A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.

Abstract translation: 一种用于制造电连接封装和其它部件的端子金属焊盘结构的方法。 更具体地，本发明包括用于制造多个耐腐蚀端子金属焊盘的方法。 每个焊盘包括一个包含铜的基座，其被封装在一系列连续电镀的金属封装膜中以产生耐腐蚀的端子金属焊盘。

公开(公告)号：US6143117A

公开(公告)日：2000-11-07

申请号：US460484

申请日：1999-12-14

Applicant: Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

Inventor： Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

IPC: B32B43/00 ,  B44C1/165 ,  H01L21/68 ,  H05K3/00 ,  H05K3/02 ,  H05K3/28 ,  H05K3/46

CPC classification number: B32B43/00 ,  H01L21/6835 ,  H05K3/025 ,  H05K3/4614 ,  B32B2310/0843 ,  B32B2311/00 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/3025 ,  H05K2201/09527 ,  H05K2201/10666 ,  H05K2203/016 ,  H05K2203/107 ,  H05K3/007 ,  H05K3/28 ,  H05K3/4623 ,  H05K3/467 ,  Y10S156/922 ,  Y10S438/94 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T428/12528 ,  Y10T428/12583

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.

Abstract translation: 用于从主载体制造和释放薄膜结构以进一步处理的工艺。 薄膜结构建立在设置在电介质层上的金属互连上，其又沉积在主载体上。 薄膜结构和金属互连通过限定在金属互连和电介质膜之间的释放界面从电介质层和初级载体释放。 通过激光烧蚀或切割来干扰界面来实现释放。 本发明的方法具有至少三个具体应用：（1）可以释放薄膜结构和金属互连以产生独立的膜; （2）薄膜结构和金属互连可以层压在永久性基板上（当构建顶部向下结构时）然后释放; （3）可以将薄膜结构转移到二次临时载体（当构建顶侧上部结构）进行进一步的加工和测试时，在释放薄膜结构和金属互连之前转移到永久基板。

公开(公告)号：US6036809A

公开(公告)日：2000-03-14

申请号：US250882

申请日：1999-02-16

Applicant: Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

Inventor： Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

IPC: B32B43/00 ,  B44C1/165 ,  H01L21/68 ,  H05K3/00 ,  H05K3/02 ,  H05K3/28 ,  H05K3/46 ,  B32B31/00 ,  H01B13/00 ,  H01L29/12 ,  B32B4/00

CPC classification number: B32B43/00 ,  H01L21/6835 ,  H05K3/025 ,  H05K3/4614 ,  B32B2310/0843 ,  B32B2311/00 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/3025 ,  H05K2201/09527 ,  H05K2201/10666 ,  H05K2203/016 ,  H05K2203/107 ,  H05K3/007 ,  H05K3/28 ,  H05K3/4623 ,  H05K3/467 ,  Y10S156/922 ,  Y10S438/94 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T428/12528 ,  Y10T428/12583

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.

Abstract translation: 用于从主载体制造和释放薄膜结构以进一步处理的工艺。 薄膜结构建立在设置在电介质层上的金属互连上，其又沉积在主载体上。 薄膜结构和金属互连通过限定在金属互连和电介质膜之间的释放界面从电介质层和初级载体释放。 通过激光烧蚀或切割来干扰界面来实现释放。 本发明的方法具有至少三个具体应用：（1）可以释放薄膜结构和金属互连以产生独立的膜; （2）薄膜结构和金属互连可以层压在永久性基板上（当构建顶部向下结构时）然后释放; （3）可以将薄膜结构转移到二次临时载体（当构建顶侧上部结构）进行进一步的加工和测试时，在释放薄膜结构和金属互连之前转移到永久基板。

公开(公告)号：US5310625A

公开(公告)日：1994-05-10

申请号：US101261

申请日：1993-08-03

Applicant: Marie Angelopoulos ,  Daniel G. Berger ,  Jeffrey W. Labadie ,  Eric D. Perfecto ,  Martha I. Sanchez ,  Sally A. Swanson ,  Willi Volksen

Inventor： Marie Angelopoulos ,  Daniel G. Berger ,  Jeffrey W. Labadie ,  Eric D. Perfecto ,  Martha I. Sanchez ,  Sally A. Swanson ,  Willi Volksen

IPC: G03F7/027 ,  C08F283/04 ,  C08G73/10 ,  G03F7/028 ,  G03F7/038 ,  G03F7/38 ,  G03F7/40 ,  H01L21/027 ,  G03C5/56

CPC classification number: C08G73/1025 ,  C08F283/04 ,  G03F7/0387 ,  G03F7/40

Abstract: The present invention relates to an improved process for forming negative tone images of photosensitive polyimides on a substrate having improved wall angles.

Abstract translation: 本发明涉及一种用于在具有改进的壁角的基板上形成感光性聚酰亚胺的负色调图像的改进方法。

公开(公告)号：US20140021607A1

公开(公告)日：2014-01-23

申请号：US13552792

申请日：2012-07-19

Applicant: Charles L. Arvin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Jennifer D. Schuler

Inventor： Charles L. Arvin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Jennifer D. Schuler

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13139 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16237 ,  H01L2224/81193 ,  H01L2224/81439 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/05552

Abstract: An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side.

Abstract translation: 公开了一种集成电路（IC）芯片，其包括用于连接到封装衬底的焊料结构，IC芯片封装及其形成方法。 在一个实施例中，提供一种IC芯片，其包括具有设置在晶片上方的多个焊料结构的晶片。 球限制冶金（BLM）层设置在多个焊料结构和晶片之间。 多个焊料结构中的至少一个具有第一直径和第一高度，并且至少一个其它焊料结构具有第二直径和第二高度。 焊料结构的不同高度和体积有助于在IC芯片侧而不是封装侧进行芯片连接改进的焊料体积补偿。

公开(公告)号：US20120305633A1

公开(公告)日：2012-12-06

申请号：US13154412

申请日：2011-06-06

Applicant: Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

Inventor： Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

IPC: B23K1/20 ,  B23K31/02

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: Solder bumps of uniform height are provided on a substrate through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned layer of photoresist. Solder is injected over the pillars or BLM, filling the channels. The solder, which does not contain flux, is allowed to solidify. It forms a plurality of solder structures (bumps) of equal heights. Solder injection and solidification are preferably carried out in a nitrogen environment or a forming gas environment. Molten solder can be injected in channels formed in round wafers without spillage using a carrier assembly that accommodates such wafers and a fill head.