公开(公告)号：US07485501B2

公开(公告)日：2009-02-03

申请号：US11265337

申请日：2005-11-02

申请人： Hem Takiar ,  Shrikar Bhagath ,  Chin-Tien Chiu

发明人： Hem Takiar ,  Shrikar Bhagath ,  Chin-Tien Chiu

IPC分类号： H01L21/44

CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method is disclosed for forming semiconductor packages by a process of punching and cutting the packages from a panel of integrated circuits. During an encapsulation process for encapsulating the packages in a molding compound, portions of the panel may be left free of molding compound. Portions of the panel left free of molding compound may subsequently be punched from the panel. These punched areas may define chamfers, notches or a variety of other curvilinear, rectilinear or irregular shapes in the outer edges of the finished semiconductor package. After the panel is punched, the integrated circuits may be singulated. By punching areas from the panel, and then cutting along straight edges, a simple, effective and cost efficient method is disclosed for obtaining finished semiconductor packages of a variety of desired shapes.

摘要翻译： 公开了一种用于通过从集成电路板冲压和切割封装件的工艺来形成半导体封装件的方法。 在将包装封装在模塑料中的封装过程中，面板的部分可以不含模塑料。 随后可以从面板冲压出没有模塑料的板的部分。 这些冲压区域可以在完成的半导体封装的外边缘中限定倒角，凹口或各种其它曲线，直线形或不规则形状。 在打孔面板之后，可以将集成电路分割。 通过从面板冲压区域，然后沿直边切割，公开了一种简单，有效和成本有效的方法来获得各种期望形状的成品半导体封装。

公开(公告)号：US20070152215A1

公开(公告)日：2007-07-05

申请号：US11321663

申请日：2005-12-29

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L24/73 ,  H01L22/34 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the solder bumps get flattened out to be generally flush with and exposed on a surface of the semiconductor package. These exposed portions of the solder bumps form the test pads by which the finished package may be tested.

公开(公告)号：US09064836B1

公开(公告)日：2015-06-23

申请号：US12852643

申请日：2010-08-09

申请人： Chin-Tien Chiu ,  Shrikar Bhagath ,  Yuang Zhang ,  Lu Zhong ,  Kaiyou Qian

发明人： Chin-Tien Chiu ,  Shrikar Bhagath ,  Yuang Zhang ,  Lu Zhong ,  Kaiyou Qian

IPC分类号： H01L29/34 ,  H01L21/02

CPC分类号： H01L29/34 ,  B24B7/228 ,  B24B37/107 ,  H01L21/02024 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3221 ,  H01L25/065 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor wafer, die and semiconductor package formed therefrom are disclosed, where the inactive surface of the wafer has an extrinsic gettering pattern formed from a texturing process. In examples, the texturing process follows a polishing process that removes stress concentration point from the inactive surface of the wafer.

摘要翻译： 公开了从其形成的半导体晶片，管芯和半导体封装，其中晶片的非活性表面具有由纹理化工艺形成的外在吸气图案。 在实例中，纹理化处理遵循从晶片的非活性表面去除应力集中点的抛光工艺。

公开(公告)号：US08294251B2

公开(公告)日：2012-10-23

申请号：US12165320

申请日：2008-06-30

申请人： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

发明人： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

IPC分类号： H01L23/02

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04953 ,  H01L2924/078 ,  H01L2924/10155 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/3512 ,  H01L2924/00

摘要： A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.

摘要翻译： 公开了一种半导体管芯和由其形成的低剖面半导体封装。 半导体封装可以包括安装到衬底的至少第一和第二堆叠半导体管芯。 第一和/或第二半导体管芯可以沿着半导体管芯的侧边缘通过半导体管芯的底表面被制造成具有局部空腔。 一个侧面中的一个或多个局部空腔占据整个侧面。 因此，局部空腔允许半导体芯片的低高度堆叠，同时为每个模具提供高度的结构完整性，以防止在制造期间模头边缘的破裂或断裂。

公开(公告)号：US20110024881A1

公开(公告)日：2011-02-03

申请号：US12906523

申请日：2010-10-18

申请人： Shrikar Bhagath ,  Hem Takiar

发明人： Shrikar Bhagath ,  Hem Takiar

IPC分类号： H01L29/06 ,  H01L23/48

CPC分类号： H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N.

摘要翻译： 一种半导体器件，其包括在被填充有薄膜的裸片堆叠中的半导体管芯。 一旦半导体管芯形成，它们可以被堆叠和互连。 互连可能在芯片堆叠中的半导体管芯之间留下小的空间。 该空间有利地使用气相沉积方法完全填充，其中涂层作为蒸汽沉积，该蒸汽流过管芯堆叠的所有表面，包括进入堆叠中的管芯之间的空间。 然后，蒸汽沉积在模具之间和周围的表面上并形成完全填充模具堆叠中的模具之间的空间的膜。 在气相沉积填充过程中使用的材料可以例如是聚对二甲苯聚合物族的成员，并且在实施方案中可以是聚对二甲苯-N。

公开(公告)号：US20090325344A1

公开(公告)日：2009-12-31

申请号：US12165340

申请日：2008-06-30

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L21/60

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/01047 ,  H01L2224/85186 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00015

摘要： A method of fabricating a low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.

摘要翻译： 公开了一种制造低轮廓半导体封装件的方法，该方法至少包括安装到衬底上的第一和第二层叠半导体管芯。 第一和/或第二半导体管芯可以被制造成多个再分布焊盘，其形成在多个接合焊盘上并电耦合到多个接合焊盘。 在半导体管芯从晶片形成和切割之后，可以使用根据本发明的低剖面反向引线接合将管芯安装到衬底上。 特别地，在传统的反向接合工艺中，可以在导线和再分布垫之间形成楔形键，而不必在芯片接合焊盘上使用第二线接合球。

公开(公告)号：US20090321950A1

公开(公告)日：2009-12-31

申请号：US12165320

申请日：2008-06-30

申请人： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

发明人： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

IPC分类号： H01L23/49

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04953 ,  H01L2924/078 ,  H01L2924/10155 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/3512 ,  H01L2924/00

摘要： A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.

摘要翻译： 公开了一种半导体管芯和由其形成的低剖面半导体封装。 半导体封装可以包括安装到衬底的至少第一和第二堆叠半导体管芯。 第一和/或第二半导体管芯可以沿着半导体管芯的侧边缘通过半导体管芯的底表面被制造成具有局部空腔。 一个侧面中的一个或多个局部空腔占据整个侧面。 因此，局部空腔允许半导体芯片的低高度堆叠，同时为每个模具提供高度的结构完整性，以防止在制造期间模头边缘的破裂或断裂。

公开(公告)号：US20090134502A1

公开(公告)日：2009-05-28

申请号：US12363311

申请日：2009-01-30

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L23/495 ,  H05K7/00

CPC分类号： H01L23/49541 ,  G06K19/07732 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.

摘要翻译： 公开了一种用于形成具有曲线形状的引线框半导体封装的引线框设计。 引线框可以各自包括对应于精加工和分割半导体封装中的曲线边缘的一个或多个曲线槽。 在封装之后，面板上的集成电路封装可以通过将集成电路从引线框板切割成多个单独的集成电路封装而被分割。 引线框中的槽有利地允许使用仅制成直线切割的锯片来切割每个引线框。

公开(公告)号：US07495255B2

公开(公告)日：2009-02-24

申请号：US11777027

申请日：2007-07-12

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L21/66

CPC分类号： H01L24/73 ,  H01L22/34 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the solder bumps get flattened out to be generally flush with and exposed on a surface of the semiconductor package. These exposed portions of the solder bumps form the test pads by which the finished package may be tested.

摘要翻译： 公开了半导体封装，其包括在制造期间由固定到半导体封装的焊料凸块形成的测试焊盘。 当包装被封装时，由于在封装过程中施加在包装上的压力，焊料凸块的部分变平整，以与半导体封装的表面大致平齐并暴露。 焊料凸块的这些暴露部分形成测试焊盘，通过该测试焊盘可以测试成品封装。

公开(公告)号：US20080237887A1

公开(公告)日：2008-10-02

申请号：US11693651

申请日：2007-03-29

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L23/52

CPC分类号： H01L24/85 ,  H01L23/49575 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/78302 ,  H01L2224/83855 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/48471 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad.

摘要翻译： 公开了一种半导体器件，其包括芯片接合焊盘，其加强以允许偏移堆叠焊盘的引线接合，即使在紧密偏移配置中。 在将第一裸片固定到基底之后，可以在第一衬底的一些或全部芯片接合焊盘上提供一层或多层电导体，以提高焊盘的高度。 导电层可以例如是使用已知的引线键合毛细管沉积在第一衬底的管芯接合焊盘上的导电球。 此后，可以添加第二管芯，并且可以使用在第一半导体管芯接合焊盘的凸起表面上安装引线接合球的公知的引线接合毛细管来实现第一管芯的引线接合。