公开(公告)号：US07619305B2

公开(公告)日：2009-11-17

申请号：US11889693

申请日：2007-08-15

申请人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

发明人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

IPC分类号： H01L23/02 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/488 ,  H01L23/485

CPC分类号： H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/83856 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0367 ,  H05K2201/0379 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.

公开(公告)号：US20090278256A1

公开(公告)日：2009-11-12

申请号：US12118052

申请日：2008-05-09

申请人： Wen-Jeng FAN

发明人： Wen-Jeng FAN

IPC分类号： H01L23/498

CPC分类号： H01L23/13 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop. The stepwise depression can accommodate the die-attaching material to control bleeding contaminations.

摘要翻译： 显示出具有增强的球端子移动性的半导体封装。 芯片通过芯片附着材料附着到基板上，其中基板在被覆表面上具有至少一个阶梯式凹陷，以使基板厚度从模具安装区域的中心线逐渐减小到 基质。 模具附着材料填充在阶梯式凹陷中。 因此，芯片的截面角下的模具安装材料的厚度变厚，使得离开模具安装区域的中心线的一排球端子能够在不改变外观的情况下具有更大的移动性 半导体封装的尺寸，厚度，以及球形端子的放置平面。 因此，位于半导体封装的边缘或角落附近的一排球端子可以承受较大的应力，而不会产生球裂纹或球掉落。 阶梯式凹陷可以容纳模具附着材料以控制出血污染。

公开(公告)号：US20090160041A1

公开(公告)日：2009-06-25

申请号：US12071611

申请日：2008-02-25

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/498

CPC分类号： H01L23/5386 ,  H01L21/565 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate package structure is disclosed herein. The substrate package structure includes a packaging substrate provided with a plurality of chip carriers set at one surface of the packaging substrate, wherein those chip carriers are formed by intersecting a plurality of cutting streets; a plurality of through holes set at those cutting streets and set around those chip carriers; and a plurality of molding areas set on another surface of the packaging substrate and opposite to those chip carriers, wherein those molding areas are adjacent to those through holes. Hence, those through holes may be flowed by the molding compound to form a plurality of molding bumps around those chip carriers so as to improve the crack problem of the chip and/or the substrate.

摘要翻译： 本文公开了一种衬底封装结构。 衬底封装结构包括设置有设置在封装衬底的一个表面处的多个芯片载体的封装衬底，其中这些芯片载体通过与多个切割街道相交而形成; 设置在那些切割街道处的多个通孔并围绕这些芯片载体设置; 以及设置在所述包装基板的另一表面上且与所述芯片载体相对的多个模制区域，其中所述模制区域与所述通孔相邻。 因此，这些通孔可以通过模塑料流动，以在这些芯片载体周围形成多个模制凸块，从而改善芯片和/或基板的裂纹问题。

公开(公告)号：US20090127678A1

公开(公告)日：2009-05-21

申请号：US11984771

申请日：2007-11-21

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles.

摘要翻译： 半导体封装的堆叠组件主要包括多个堆叠的半导体封装。 每个半导体封装包括密封剂，至少芯片和引线框架的多个外部引线，其中外部引线从密封剂的多个侧面暴露和延伸。 当封装分割时，上半导体封装的每个外部引线具有U形切割端。 U形切割端被构造成用于通过焊接材料锁定到U形切割端的下半导体封装的相应外部引线的焊接部分和焊接部分。 因此，堆叠组件具有更大的焊接面积和更强的导线可靠性，以增强焊接点以抵抗冲击，热冲击和热循环的影响。

公开(公告)号：US20090096070A1

公开(公告)日：2009-04-16

申请号：US12068623

申请日：2008-02-08

申请人： Wen-Jeng Fan ,  Yi-Ling Liu

发明人： Wen-Jeng Fan ,  Yi-Ling Liu

IPC分类号： H01L23/495 ,  H05K7/18

CPC分类号： H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from the fingers. A chip is disposed on the substrate and is electrically connected to the fingers. An encapsulant is completely filled the peripheral slot. The peripheral slot can enhance the mold flow and eliminate the mold flash. The shape of the dummy metal pattern aligned to the peripheral slot is used to offer stiffening edges to prevent the substrate from warpage and from breakage at peripheries, to enhance the thermal stress resistance due to thermal cycles, and to avoid damages to the chip.

摘要翻译： 使用特殊设计的基板显露半导体封装。 衬底具有多个指状物，虚拟金属图案，以及穿透衬底的至少一个外围槽。 虚设金属图案与外围槽的两个相对的侧对齐并且与手指电隔离。 芯片设置在基板上并与手指电连接。 密封剂完全填充外围槽。 外围槽可以增强模具流动，消除模具闪光。 与外围槽对准的虚设金属图案的形状用于提供加强边缘，以防止基板翘曲并在周边断裂，从而提高由于热循环引起的热应力阻力，并避免损坏芯片。

公开(公告)号：US20090026599A1

公开(公告)日：2009-01-29

申请号：US11878891

申请日：2007-07-27

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/02

CPC分类号： H05K1/0271 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H05K1/181 ,  H05K2201/09145 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2201/2009 ,  H05K2203/1572 ,  H01L2924/00

摘要： A memory module capable of lessening shock stresses, primarily comprises a multi-layer printed circuit board (PCB), a plurality of memory packages, and a stress-buffering layer. The memory packages are disposed at least on one of the rectangular surfaces of the PCB. The stress-buffering layer is disposed at least on both short sides of the PCB and extended to the two rectangular surfaces to reduce the impact stresses. Preferably, the stress-buffering layer is further disposed on the other long side of the PCB opposite to the one with disposed gold fingers.

摘要翻译： 能够减轻冲击应力的存储器模块主要包括多层印刷电路板（PCB），多个存储器封装和应力缓冲层。 存储器封装被布置在PCB的至少一个矩形表面上。 应力缓冲层至少设置在PCB的两个短边上并延伸到两个矩形表面以减小冲击应力。 优选地，应力缓冲层进一步设置在PCB的与设置的金手指相对的另一长边上。

公开(公告)号：US20080179731A1

公开(公告)日：2008-07-31

申请号：US11657715

申请日：2007-01-25

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/13

CPC分类号： H05K1/0271 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H05K1/117 ,  H05K2201/09909 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2201/2009 ,  H01L2924/00012 ,  H01L2924/00

摘要： An anti-impact memory module mainly comprises a multi-layer PWB (Printed Wiring Board), a plurality of memory packages and a plurality of first anti-impact bars. The PWB has two longer sides and two shorter sides. A plurality of gold fingers are disposed along one of the longer sides. The first anti-impact bars are disposed on one surface of the PWB and adjacent to the two shorter sides, which are higher than the memory packages in height. Preferably, at least a second anti-impact bar is formed at another longer side far away from the gold fingers. The first anti-impact bars and/or the second anti-impact bar can be utilized to cushion impact force for preventing the memory module product from damaging while fallen accidentally.

摘要翻译： 防冲击存储器模块主要包括多层PWB（印刷线路板），多个存储器封装和多个第一抗冲击棒。 电路板有两个长边和两个短边。 多个金指沿着较长的一侧设置。 第一个防冲击杆设置在PWB的一个表面上，并且与两个短边相邻，这两个较短的边比高度的存储包高。 优选地，至少第二防撞杆形成在远离金手指的另一较长侧。 第一防冲击杆和/或第二防冲击杆可以用于缓冲冲击力，以防止存储模块产品在意外下降时受到损坏。

公开(公告)号：US20080054494A1

公开(公告)日：2008-03-06

申请号：US11514349

申请日：2006-09-01

申请人： Cheng-Ping Chen ,  Wen-Jeng Fan

发明人： Cheng-Ping Chen ,  Wen-Jeng Fan

IPC分类号： H01L23/28

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package mainly includes a substrate having slot(s), a chip, a protective encapsulant, a stiffening encapsulant, and a plurality of external terminals. The Young's modulus of the stiffening encapsulant is greater than the one of the protective encapsulant and the curing shrinkage of the stiffening encapsulant is smaller than the one of the protective encapsulant. The protective encapsulant is formed on one of the surfaces of the substrate for encapsulating the chip. The stiffening encapsulant protrudes from the other surface of the substrate where the external terminals are disposed. Moreover, the stiffening encapsulant is formed inside the slot and is contacted with the chip. Since the stiffening encapsulant is embedded and formed inside the slot, therefore, the contact area of the stiffening encapsulant with the substrate is increased to enhance the warpage resistance of the IC package.

摘要翻译： IC封装主要包括具有槽的衬底，芯片，保护性密封剂，加强密封剂和多个外部端子。 加强密封剂的杨氏模量大于保护性密封剂中的一种，并且硬化密封剂的固化收缩率小于保护性密封剂中的一种。 保护性密封剂形成在用于封装芯片的衬底的一个表面上。 加强密封剂从设置有外部端子的基板的另一个表面突出。 此外，加强密封剂形成在槽内并与芯片接触。 由于加强密封剂嵌入并形成在槽内，因此，加强密封剂与基板的接触面积增大，以提高IC封装的翘曲阻力。

公开(公告)号：US08304917B2

公开(公告)日：2012-11-06

申请号：US12630658

申请日：2009-12-03

申请人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ronald Takaoiwata

发明人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ronald Takaoiwata

IPC分类号： H01L23/528

CPC分类号： H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A multi-chip stacked package and its mother chip to save an interposer are revealed. The mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.

摘要翻译： 揭示了一种多芯片堆叠封装及其母芯片来节省内插器。 母芯片是由半导体层和有机层组成的两层结构，其中再分配层嵌入有机层中，多个第一端子和多个第二端子设置在再分配层上并从有机层暴露 层。 母芯片倒装芯片安装在基板上。 子芯片的有源面与有机层接触，子芯片的接合焊盘与第一端子接合。 此外，多个电连接部件将第二端子电连接到基板。 在多芯片堆叠封装中，可以以更薄的整体封装厚度以及受控的封装翘曲消除中介层。

公开(公告)号：US08053676B2

公开(公告)日：2011-11-08

申请号：US12191645

申请日：2008-08-14

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H05K1/03 ,  H05K7/00

CPC分类号： H05K3/242 ,  H05K3/0052 ,  H05K2201/09254

摘要： A substrate panel primarily comprises a plurality of substrate strips arranged in an array, one or more current input lines, a plurality of cascaded lines connecting between the substrate strips, and a current input buffer gate. Current input lines connect a current input side of the substrate panel to the adjacent substrate strips. The current input buffer gate has a frame around the substrate strips and a plurality of meshes where the frame intersects with the current input lines and the meshes intersect with the cascaded lines with both ends of the meshes connecting to the frame. Therefore, the current can be evenly distributed to each substrate strip during plating processes to improve the issues of different plating thicknesses and different plating roughness caused by different current densities and to protect the internal circuits inside the substrate strips from the damages due to current surges and unstable voltages.

摘要翻译： 衬底面板主要包括布置成阵列的多个衬底条，一个或多个电流输入线，连接在衬底条之间的多条级联线和电流输入缓冲门。 电流输入线将基板面板的电流输入侧连接到相邻的基板条。 当前输入缓冲器门具有围绕衬底条的框架以及框架与当前输入线相交的多个网格，并且网格与连接到框架的网格的两端的级联线相交。 因此，电镀过程中电流可以均匀地分布到每个衬底条上，以改善由不同电流密度引起的不同电镀厚度和不同电镀粗糙度的问题，并保护衬底条内部的电路免受由于电流浪涌引起的损坏， 电压不稳定