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    Multi-chip stack structure having through silicon via and method for fabrication the same
    21.
    发明申请
    Multi-chip stack structure having through silicon via and method for fabrication the same 审中-公开
    具有硅通孔的多芯片堆叠结构及其制造方法

    公开(公告)号：US20090032928A1

    公开(公告)日：2009-02-05

    申请号：US12220995

    申请日：2008-07-30

    申请人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

    发明人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

    IPC分类号： H01L23/52 ,  H01L21/00

    CPC分类号： H01L29/0657 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599

    摘要： The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.

    摘要翻译： 本发明公开了一种通过硅通孔的多芯片堆叠结构及其制造方法。 该方法包括：提供具有多个第一芯片的晶片; 在每个所述第一芯片的第一表面上形成多个孔，并形成对应于所述孔的金属柱和焊盘，以形成贯穿硅通孔（TSV）结构; 在所述第一芯片的每一个的第二表面上形成至少一个凹槽以暴露所述TSV结构的所述金属柱，以允许至少一个第二芯片堆叠在所述第一芯片上，被接收在所述凹槽中并电连接到 从槽露出的金属柱; 用绝缘材料填充凹槽以封装第二芯片; 将导电元件安装在每个第一芯片的第一表面的焊盘上并分离晶片; 并且经由导电元件将堆叠的第一和第二芯片安装并电连接到芯片载体。 不是完全变薄但包括多个第一芯片的晶片在制造过程中切断了承载目的，从而解决了面临现有技术需要重复使用的问题，即复杂的工艺，高成本和粘合剂层污染 的载体板和用于垂直堆叠多个芯片的粘合剂层，并将堆叠的芯片安装在芯片载体上。

    Stacked package structure and fabrication method thereof
    22.
    发明申请
    Stacked package structure and fabrication method thereof 审中-公开
    堆叠封装结构及其制造方法

    公开(公告)号：US20080283994A1

    公开(公告)日：2008-11-20

    申请号：US12152687

    申请日：2008-05-16

    申请人： Ho-Yi Tsai ,  Chien-Ping Huang ,  Jung-Pin Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao

    发明人： Ho-Yi Tsai ,  Chien-Ping Huang ,  Jung-Pin Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao

    IPC分类号： H01L23/49 ,  H01L21/56

    CPC分类号： H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/1411 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/3436 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing the stackable solder pads from the encapsulant, thus forming a lower-layer semiconductor package; forming conductive bumps on at least one stackable solder pad by means of wire bonding such that at least one upper-layer semiconductor package can be mounted via solder balls on the conductive bumps and the stackable solder pads of the lower-layer semiconductor package to form a stacked package structure, wherein, stacking height of the solder balls and the conductive bumps is greater than height of the encapsulant of the lower-layer semiconductor package, thus, when stacking fine pitch semiconductor packages or when warps occur to the upper-layer semiconductor package or the lower-layer semiconductor package, the conductive bumps can compensate for inadequate height caused by solder ball collapse or fill up gaps between the solder balls and the stackable solder pads caused by warps, thereby allowing the solder balls to be able to effectively contact and wet on the substrate of the lower-layer semiconductor package.

    摘要翻译： 公开了一种堆叠封装结构及其制造方法，包括提供一种具有形成在其表面上的多个可叠置焊料焊盘的衬底，用于允许至少一个半导体芯片电连接到衬底; 形成用于封装半导体芯片的密封剂，并进一步从可密封剂暴露可堆叠的焊盘，从而形成下层半导体封装; 通过引线接合在至少一个可堆叠的焊盘上形成导电凸块，使得至少一个上层半导体封装可以经由焊球安装在导电凸块和下层半导体封装的可堆叠焊盘上，以形成 堆叠的封装结构，其中，焊球和导电凸块的堆叠高度大于下层半导体封装的密封剂的高度，因此，当堆叠精细间距半导体封装时或当上行半导体封装发生翘曲时 或下层半导体封装，导电凸块可以补偿由焊球塌陷引起的不适当的高度，或填充由经线引起的焊球和可堆叠焊盘之间的间隙，从而允许焊球能够有效地接触和 在下层半导体封装的衬底上湿润。

    Multi-chip stack structure and fabrication method thereof
    24.
    发明申请
    Multi-chip stack structure and fabrication method thereof 有权
    多芯片堆叠结构及其制造方法

    公开(公告)号：US20080224289A1

    公开(公告)日：2008-09-18

    申请号：US12077003

    申请日：2008-03-13

    申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC分类号： H01L23/495 ,  H01L21/00

    CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

    Method for reducing size of semiconductor unit in packaging process
    27.
    发明授权
    Method for reducing size of semiconductor unit in packaging process 失效
    减少包装过程中半导体单元尺寸的方法

    公开(公告)号：US06720270B1

    公开(公告)日：2004-04-13

    申请号：US09660753

    申请日：2000-09-13

    申请人： Chin-Huang Chang

    发明人： Chin-Huang Chang

    IPC分类号： H01L21302

    CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L24/10 ,  H01L2221/6834 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2224/0401

    摘要： The present invention provides different schemes for reducing the size (such as thickness) of at least a semiconductor unit (such as an IC chip) which is to be packaged. It replaces, in packaging at least a semiconductor unit, conventional grinding processes by etching schemes, particularly when the thickness of the semiconductor unit approximates an expected specification. The etching process may be embodied in a way that a semiconductor unit attached to a carrier such as a substrate, or placed onto a seating apparatus such as a chip tray, and properly shielded, is etched by means of using gas such as plasma, or beams of light. The semiconductor unit packaged according to the scheme provided by the present invention can thus be immunized against the failure resulting from die crack or back-side chipping.

    摘要翻译： 本发明提供了用于减少至少要包装的半导体单元（例如IC芯片）的尺寸（例如厚度）的不同方案。 在将至少一个半导体单元封装在一起时，代替了通过蚀刻方案的常规研磨工艺，特别是当半导体单元的厚度接近预期规格时。 蚀刻工艺可以通过使用诸如等离子体之类的气体来蚀刻附接到诸如衬底的载体的半导体单元或放置在诸如芯片托盘的座位装置上并被适当地屏蔽的半导体单元的方式，或者 光束。 因此，可以根据本发明提供的方案包装的半导体单元免受由于模头裂纹或背面切屑引起的故障的影响。

    MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA
    29.
    发明申请
    MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA 审中-公开
    通过硅的多芯片堆叠结构

    公开(公告)号：US20110227226A1

    公开(公告)日：2011-09-22

    申请号：US13151823

    申请日：2011-06-02

    申请人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

    发明人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

    IPC分类号： H01L23/48

    CPC分类号： H01L29/0657 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599

    摘要： The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.

    摘要翻译： 本发明公开了一种通过硅通孔的多芯片堆叠结构及其制造方法。 该方法包括：提供具有多个第一芯片的晶片; 在每个所述第一芯片的第一表面上形成多个孔，并形成对应于所述孔的金属柱和焊盘，以形成贯穿硅通孔（TSV）结构; 在所述第一芯片的每一个的第二表面上形成至少一个凹槽以暴露所述TSV结构的所述金属柱，以允许至少一个第二芯片堆叠在所述第一芯片上，被接收在所述凹槽中并电连接到 从槽露出的金属柱; 用绝缘材料填充凹槽以封装第二芯片; 将导电元件安装在每个第一芯片的第一表面的焊盘上并分离晶片; 并且经由导电元件将堆叠的第一和第二芯片安装并电连接到芯片载体。 不是完全变薄但包括多个第一芯片的晶片在制造过程中切断了承载目的，从而解决了面临现有技术需要重复使用的问题，即复杂的工艺，高成本和粘合剂层污染 的载体板和用于垂直堆叠多个芯片的粘合剂层，并将堆叠的芯片安装在芯片载体上。

    SENSOR SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
    30.
    发明申请
    SENSOR SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME 审中-公开
    传感器半导体封装及其制造方法

    公开(公告)号：US20090166831A1

    公开(公告)日：2009-07-02

    申请号：US12344988

    申请日：2008-12-29

    申请人： Tse-Wen Chang ,  Chang-Yueh Chan ,  Chin-Huang Chang ,  Chih-Ming Huang

    发明人： Tse-Wen Chang ,  Chang-Yueh Chan ,  Chin-Huang Chang ,  Chih-Ming Huang

    IPC分类号： H01L23/04 ,  H01L21/50

    CPC分类号： H01L27/14618 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L27/14683 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

    摘要： This invention provides a sensor semiconductor package and a method for fabricating the same. The method includes: mounting on a substrate a sensor chip having a sensor area; electrically connecting the sensor chip and the substrate by means of bonding wires; forming on a transparent member an adhesive layer with an opening corresponding in position to the sensor area; and mounting the transparent member on the substrate via the adhesive layer while heating the substrate, such that the adhesive layer melts, to thereby encapsulate the periphery of the sensor chip and the bonding wires while exposing the sensor area from the adhesive layer. Thus, the sensor area is sealed by the transparent member cooperative with the adhesive layer, making the sensor semiconductor package thus-obtained dam-free, light, thin, and compact, and incurs low process costs. Also, the product reliability is enhanced since the bonding wires are encapsulated by the adhesive layer without severing concern.

    摘要翻译： 本发明提供一种传感器半导体封装及其制造方法。 该方法包括：在基板上安装具有传感器区域的传感器芯片; 通过接合线电连接传感器芯片和基板; 在透明构件上形成具有对应于传感器区域的位置的开口的粘合剂层; 并且通过粘合剂层将透明构件安装在基板上，同时加热基板，使得粘合剂层熔化，从而在将传感器区域从粘合剂层暴露出来的同时封装传感器芯片和接合线的周边。 因此，传感器区域与透明构件密封，与粘合剂层协作，使得传感器半导体封装得到无阻尼，轻薄，紧凑，并且导致低的工艺成本。 而且，由于接合线被粘合剂层封装而不会被切断，所以产品的可靠性得到提高。