公开(公告)号：US20170221764A1

公开(公告)日：2017-08-03

申请号：US15014150

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-gyu SUNG ,  Ruilong XIE ,  Chanro PARK

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

公开(公告)号：US20140353734A1

公开(公告)日：2014-12-04

申请号：US13909328

申请日：2013-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Xiuyu CAI ,  Vimal KAMINENI ,  Kangguo CHENG ,  Ali KHAKIFIROOZ

IPC: H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section.

Abstract translation: 提供具有减小的栅极和/或接触电阻的半导体结构和制造方法。 该方法包括：提供半导体器件，其包括形成半导体器件的晶体管，其中晶体管形成包括：形成用于晶体管的T形栅极，T形栅极呈垂直截面为T形; 并且在晶体管的有源区域形成倒T形的接触，所述倒T形接触件包括在横截面上具有倒T形的导电结构。

公开(公告)号：US20200083363A1

公开(公告)日：2020-03-12

申请号：US16126775

申请日：2018-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Laertis ECONOMIKOS ,  Jiehui SHU ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.

公开(公告)号：US20180301531A1

公开(公告)日：2018-10-18

申请号：US15486351

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66742

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content can be controlled such that voids created by removal of the silicon germanium have uniform dimensions, and the backfilling of such voids with gate dielectric and gate conductor layers proximate to silicon nanosheets or nanowires results in devices having a uniform effective gate length.

公开(公告)号：US20180138046A1

公开(公告)日：2018-05-17

申请号：US15351747

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven BENTLEY ,  Ruilong XIE

IPC: H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/265

CPC classification number: H01L21/28123 ,  H01L21/26513 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.

公开(公告)号：US20180096895A1

公开(公告)日：2018-04-05

申请号：US15284110

申请日：2016-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/66795

Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.

公开(公告)号：US20180012887A1

公开(公告)日：2018-01-11

申请号：US15202764

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre LABONTE ,  Ruilong XIE ,  Xunyuan ZHANG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact.

公开(公告)号：US20170352654A1

公开(公告)日：2017-12-07

申请号：US15170109

申请日：2016-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Cheng CHI

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/66795

Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

公开(公告)号：US20170053836A1

公开(公告)日：2017-02-23

申请号：US14830245

申请日：2015-08-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

Abstract translation: 一种方法包括提供具有第一和第二多个翅片的基底，其上设置有第一至少一个介电材料，去除第一介电材料的上部以暴露第一和第二多个翅片的上部，去除 第一介电材料从第二多个翅片的下部分暴露以暴露第二多个翅片的下部，在第二多个翅片的至少上部暴露部分和下部暴露部分上沉积第二至少一个电介质材料， 第一多个翅片的上暴露部分，去除第二介电材料以暴露第一和第二多个翅片的上部，并且其中第一介电材料不同于第二介电材料。 所得到的结构可以用作nFET和pFET。