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    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    23.
    发明申请
    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100176479A1

    公开(公告)日：2010-07-15

    申请号：US12354480

    申请日：2009-01-15

    申请人： Sergei Postnikov ,  Thomas Schulz ,  Hans-Joachim Barth ,  Klaus von Arnim

    发明人： Sergei Postnikov ,  Thomas Schulz ,  Hans-Joachim Barth ,  Klaus von Arnim

    IPC分类号： H01L29/68 ,  H01L21/762

    CPC分类号： H01L27/11 ,  G03F7/40 ,  G03F7/7035 ,  H01L21/32139

    摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.

    摘要翻译： 一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在 抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有 初始宽度。 该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分 硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。

    Cooling Structures and Methods
    25.
    发明申请
    Cooling Structures and Methods 有权
    冷却结构与方法

    公开(公告)号：US20100127390A1

    公开(公告)日：2010-05-27

    申请号：US12275731

    申请日：2008-11-21

    申请人： Hans-Joachim Barth

    发明人： Hans-Joachim Barth

    IPC分类号： H01L23/473 ,  F28F7/00 ,  B23P17/00 ,  H01L23/467

    CPC分类号： H01L23/473 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

    摘要： Cooling structures and methods, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a cooling structure for a semiconductor device includes at least one channel defined between a first workpiece and a second workpiece. The second workpiece is bonded to the first workpiece. The at least one channel is adapted to retain a fluid.

    摘要翻译： 公开了冷却结构和方法，制造半导体器件的方法和半导体器件。 在一个实施例中，用于半导体器件的冷却结构包括限定在第一工件和第二工件之间的至少一个通道。 第二工件结合到第一工件。 至少一个通道适于保持流体。

    MIM Capacitors
    26.
    发明申请
    MIM Capacitors 有权
    MIM电容器

    公开(公告)号：US20080290459A1

    公开(公告)日：2008-11-27

    申请号：US12182901

    申请日：2008-07-30

    申请人： Hans-Joachim Barth ,  Petra Felsner ,  Erdem Kaltalioglu ,  Gerald R. Friese

    发明人： Hans-Joachim Barth ,  Petra Felsner ,  Erdem Kaltalioglu ,  Gerald R. Friese

    IPC分类号： H01L29/92

    CPC分类号： H01L28/40 ,  H01L21/28568 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/3185 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/75

    摘要： A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.

    摘要翻译： 一种用于形成MIM电容器的方法和由其形成的MIM电容器器件。 优选实施例包括在包括MIM电容器底板的晶片上选择性地形成第一盖层，以及在MIM电容器底板上沉积绝缘层。 用MIM电容器顶板图案对绝缘层进行构图，并且在图案化绝缘层上沉积MIM电介质材料。 在MIM介电材料上沉积导电材料，并且平坦化晶片以从绝缘层的顶表面去除导电材料和MIM电介质材料，并形成MIM电容器顶板。 在MIM电容器顶板上选择性地形成第二盖层。

    Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement
    27.
    发明申请
    Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement 有权
    用于制造具有增加的电容耦合和相关联的互连布置的互连装置的方法

    公开(公告)号：US20070042542A1

    公开(公告)日：2007-02-22

    申请号：US11205767

    申请日：2005-08-16

    申请人： Hans-Joachim Barth ,  Jurgen Holz

    发明人： Hans-Joachim Barth ,  Jurgen Holz

    IPC分类号： H01L21/8242

    CPC分类号： H01L23/5223 ,  H01L21/2885 ,  H01L21/76877 ,  H01L27/0805 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/107 ,  H01L2924/00

    摘要： A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is completely filled by a first interconnect. The trench structure of the capacitor region is only partially filled by a first capacitor electrode and is completely filled by a capacitor dielectric and a second capacitor electrode. In a second dielectric formed thereon, a second interconnect with a contact via is formed, which is connected to the second capacitor electrode.

    摘要翻译： 描述了一种用于制造具有增加的电容耦合的互连装置的方法。 在具有第一纵横比的电容器区域和与其连接的第二纵横比的互连区域的第一电介质中形成沟槽结构。 互连区域的沟槽结构由第一互连完全填充。 电容器区域的沟槽结构仅由第一电容器电极部分地填充，并且由电容器电介质和第二电容器电极完全填充。 在其上形成的第二电介质中，形成具有接触通孔的第二互连件，其连接到第二电容器电极。

    Barrier layers for conductive features
    28.
    发明申请
    Barrier layers for conductive features 有权
    阻挡层用于导电特征

    公开(公告)号：US20060202345A1

    公开(公告)日：2006-09-14

    申请号：US11079738

    申请日：2005-03-14

    申请人： Hans-Joachim Barth ,  Juergen Holz

    发明人： Hans-Joachim Barth ,  Juergen Holz

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T428/24479 ,  H01L2924/00

    摘要： Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.

    摘要翻译： 公开了用于导电特征的阻挡层及其形成方法。 第一阻挡材料沉积在绝缘材料的顶表面上，并且第二阻挡材料沉积在绝缘材料的侧壁上，其中第二阻挡材料不同于第一阻挡材料。 第一阻挡材料以第一速率诱导随后沉积的导电材料的晶粒生长，并且第二阻挡材料以第二速率诱导导电材料的晶粒生长，其中第二速率比第一速率慢。