公开(公告)号：US20150028487A1

公开(公告)日：2015-01-29

申请号：US13951554

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L25/04

CPC classification number: H01L25/04 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure.

Abstract translation: 芯片封装器件包括导电芯片载体，至少一个连接到导电芯片载体的半导体芯片，以及嵌入芯片载体，至少一个半导体芯片和无源电子器件的绝缘叠层结构。 无源电子器件包括第一结构导电层，第一结构化导电层在层压结构的表面上延伸。

公开(公告)号：US20140151862A1

公开(公告)日：2014-06-05

申请号：US14151917

申请日：2014-01-10

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

公开(公告)号：US20220148951A1

公开(公告)日：2022-05-12

申请号：US17544221

申请日：2021-12-07

Applicant: Infineon Technologies AG

Inventor： Ngoc-Hoa Huynh ,  Franz-Xaver Muehlbauer ,  Claus Waechter ,  Veronika Theyerl ,  Dominic Maier ,  Thomas Kilger ,  Saverio Trotta ,  Ashutosh Baheti ,  Georg Meyer-Berg ,  Maciej Wojnowski

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/538 ,  H01Q9/28 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q21/06 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

公开(公告)号：US10734352B2

公开(公告)日：2020-08-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US10600690B2

公开(公告)日：2020-03-24

申请号：US16102174

申请日：2018-08-13

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Claus von Waechter ,  Michael Bauer ,  Holger Doepke ,  Dominic Maier ,  Daniel Porwol ,  Tobias Schmidt

IPC: B32B37/26 ,  B32B38/10 ,  H01L21/78 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  B32B7/027 ,  H05K3/00 ,  B32B7/06

Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.

公开(公告)号：US10177112B2

公开(公告)日：2019-01-08

申请号：US15422674

申请日：2017-02-02

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Georg Meyer-Berg

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498

Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.

公开(公告)号：US10049962B2

公开(公告)日：2018-08-14

申请号：US15171364

申请日：2016-06-02

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L23/13 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065 ,  H01L23/44 ,  H01L25/07 ,  H05K7/20 ,  H05K7/08 ,  H05K7/10 ,  H05K7/02 ,  H01L23/00

Abstract: A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

公开(公告)号：US09748611B2

公开(公告)日：2017-08-29

申请号：US14311489

申请日：2014-06-23

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Jochen Dangelmaier ,  Manfred Fries ,  Juergen Hoegerl ,  Georg Meyer-Berg ,  Thomas Mueller ,  Guenther Ruhl ,  Horst Theuss ,  Mathias Vaupel

IPC: H01M10/48 ,  G01R31/36 ,  H01M6/50

CPC classification number: H01M10/48 ,  G01R31/3689 ,  H01M6/505 ,  H01M10/488

Abstract: An apparatus for determining a state of a rechargeable battery or of a battery has a sensor device and an evaluation device. The sensor device brings about an interaction between an optical signal and a part of the rechargeable battery or of the battery, which part indicates optically acquirable information about a state of the rechargeable battery or of the battery, and detects an optical signal caused by the interaction. The sensor device furthermore provides a detection signal having information about the detected optical signal. The evaluation device determines information about a state of the rechargeable battery or of the battery on the basis of the information of the detection signal. Furthermore, the evaluation device provides a state signal having the information about the determined state.

公开(公告)号：US09666499B2

公开(公告)日：2017-05-30

申请号：US13664418

申请日：2012-10-31

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/291 ,  H01L21/561 ,  H01L21/568 ,  H01L23/296 ,  H01L23/562 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles.

公开(公告)号：US09070568B2

公开(公告)日：2015-06-30

申请号：US13951556

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/12 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/16265 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/85 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A chip package includes an electrically conducting chip carrier and at least one first semiconductor chip attached to the electrically conducting chip carrier. The chip package further includes a passive component. The electrically conducting chip carrier, the at least one first semiconductor chip, and the passive component are embedded in an insulating laminate structure.

Abstract translation: 芯片封装包括导电芯片载体和连接到导电芯片载体的至少一个第一半导体芯片。 芯片封装进一步包括无源元件。 导电芯片载体，至少一个第一半导体芯片和无源部件被嵌入绝缘层压结构中。