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    CURRENT STEERING LEVEL SHIFTER
    25.
    发明申请
    CURRENT STEERING LEVEL SHIFTER 有权
    电流转向水平仪

    公开(公告)号：US20160173092A1

    公开(公告)日：2016-06-16

    申请号：US14569569

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Dinesh Somasekhar ,  Muhammad M. Khellah ,  Carlos Tokunaga ,  James W. Tschanz

    IPC: H03K19/0175

    CPC classification number: H03K19/017509

    Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.

    Abstract translation: 描述了一种装置，其包括：第一电源节点，用于提供第一电源; 第二电源节点，用于提供第二电源; 驱动器在第一电源上运行，驱动器产生输出; 以及接收器，用于在所述第二电源上操作，所述接收器接收来自所述驱动器的输出并产生电平移位输出，使得所述接收器可操作以将电流从所述第二电源转向所述第一电源。

    Architecture for on-die interconnect
    26.
    发明授权
    Architecture for on-die interconnect 有权
    管芯互连架构

    公开(公告)号：US09287208B1

    公开(公告)日：2016-03-15

    申请号：US14524622

    申请日：2014-10-27

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Ankit More ,  Dinesh Somasekhar ,  David S. Dunning

    IPC: H01L25/00 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H04L49/109 ,  H01L23/5221 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，一种装置包括：配置在半导体管芯上的多个岛，多个岛中的每一个具有多个核; 以及多个网络交换机，其配置在所述半导体管芯上并且各自与所述多个岛中的一个岛相关联，其中每个网络交换机包括多个输出端口，所述输出端口的第一组各自耦合到相关联的网络交换机 经由点对点互连的岛屿和第二组输出端口各自经由点对多点互连耦合到多个岛的相关网络交换机。 描述和要求保护其他实施例。

    Data multiplexer single phase flip-flop
    27.
    发明授权
    Data multiplexer single phase flip-flop 有权

    公开(公告)号：US12166480B2

    公开(公告)日：2024-12-10

    申请号：US17346034

    申请日：2021-06-11

    Applicant: Intel Corporation

    Inventor： Chinmay Joshi ,  Dinesh Somasekhar

    IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/0185 ,  H03K19/173 ,  H03K19/21

    Abstract: A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.

    DETECTION OF ADJACENT TWO BIT ERRORS IN A CODEWORD
    28.
    发明申请
    DETECTION OF ADJACENT TWO BIT ERRORS IN A CODEWORD 审中-公开

    公开(公告)号：US20200313694A1

    公开(公告)日：2020-10-01

    申请号：US16367511

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Wei Wu ,  Vivek Kozihikkottu ,  Dinesh Somasekhar ,  Jon Stephan ,  Kon-Woo Kwon

    IPC: H03M13/11 ,  H03M13/00 ,  H03M13/15

    Abstract: In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K−2(K−1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.

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