公开(公告)号：US11854894B2

公开(公告)日：2023-12-26

申请号：US17112697

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Valluri R. Rao ,  Patrick Morrow ,  Rishabh Mehandru ,  Doug Ingerly ,  Kimin Jun ,  Kevin O'Brien ,  Paul Fischer ,  Szuya S. Liao ,  Bruce Block

IPC: H01L21/822 ,  H01L21/306 ,  H01L21/683 ,  H01L21/8238 ,  H01L21/66 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  G01R1/073 ,  H01L25/065

CPC classification number: H01L21/8221 ,  H01L21/30625 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L22/14 ,  H01L23/528 ,  H01L23/53233 ,  H01L24/03 ,  H01L24/05 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  G01R1/07307 ,  H01L24/08 ,  H01L25/0657 ,  H01L27/1214 ,  H01L27/1222 ,  H01L29/66545 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/08147 ,  H01L2225/06565

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US11824097B2

公开(公告)日：2023-11-21

申请号：US17667493

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4175 ,  H01L21/0262 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/32115 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/45 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/6656

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US20230207560A1

公开(公告)日：2023-06-29

申请号：US17561244

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Cory C. Bomberger ,  Nicholas Minutillo ,  Ryan Cory Haislmaier ,  Yulia Tolstova ,  Yoon Jung Chang ,  Tahir Ghani ,  Szuya S. Liao ,  Anand Murthy ,  Pratik Patel

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823412

Abstract: An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device on a substrate comprising: a gate structure including a metal, the gate structure on a channel structure; a source structure in a first trench at a first side of the gate structure; a drain structure in a second trench at a second side of the gate structure; a capping layer on individual ones of the source structure and of the drain structure. The capping layer comprising a semiconductor material of a same group as a semiconductor material of a corresponding one of the source structure or of the drain structure, wherein an isotope of a p-type dopant in the capping layer represents an atomic percentage of at least about 95% of a p-type isotope content of the capping layer; and metal contact structures coupled to respective ones of the source structure and of the drain structure.

公开(公告)号：US11640988B2

公开(公告)日：2023-05-02

申请号：US17390483

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Michael L. Hattendorf ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8234

Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.

公开(公告)号：US11329138B2

公开(公告)日：2022-05-10

申请号：US15943552

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Christopher Kenyon ,  Sridhar Govindaraju ,  Chia-Hong Jan ,  Mark Liu ,  Szuya S. Liao ,  Walid M. Hafez

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

公开(公告)号：US11183592B2

公开(公告)日：2021-11-23

申请号：US16306890

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Pratik A. Patel

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092

Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.

公开(公告)号：US20200020786A1

公开(公告)日：2020-01-16

申请号：US16517220

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L21/265 ,  H01L29/51 ,  H01L29/775

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US20240088143A1

公开(公告)日：2024-03-14

申请号：US18516595

申请日：2023-11-21

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Scott B. CLENDENNING ,  Jessica TORRES ,  Lukas BAUMGARTEL ,  Kiran CHIKKADI ,  Diane LANCASTER ,  Matthew V. METZ ,  Florian GSTREIN ,  Martin M. MITAN ,  Rami HOURANI

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/538 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5384 ,  H01L23/5389 ,  H01L27/0924 ,  H01L21/823462 ,  H01L21/823871

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US11887860B2

公开(公告)日：2024-01-30

申请号：US16631345

申请日：2017-09-18

Applicant: INTEL CORPORATION

Inventor： Mehmet O. Baykan ,  Anurag Jain ,  Szuya S. Liao

IPC: H01L21/308 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L21/3088 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/20

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.

公开(公告)号：US11605632B2

公开(公告)日：2023-03-14

申请号：US17529029

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon ,  Sairam Subramanian

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/528

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.