公开(公告)号：US10431563B1

公开(公告)日：2019-10-01

申请号：US15948038

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US09748135B2

公开(公告)日：2017-08-29

申请号：US14828608

申请日：2015-08-18

Applicant: International Business Machines Corporation ,  SUSS MicroTec Photonic Systems Inc.

Inventor： Yuri M. Brovman ,  Brian M. Erwin ,  Nicholas A. Polomoff ,  Jennifer D. Schuler ,  Matthew E. Souter ,  Christopher L. Tessler

IPC: H01L21/768

CPC classification number: H01L21/76841 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03614 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

公开(公告)号：US09601423B1

公开(公告)日：2017-03-21

申请号：US14974484

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jon A. Casey ,  Brian M. Erwin ,  Steven P. Ostrander ,  Brian W. Quinlan

IPC: H01L21/02 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/16 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element.

公开(公告)号：US20160079193A1

公开(公告)日：2016-03-17

申请号：US14484313

申请日：2014-09-12

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0544 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A method including forming a copper pillar, electroplating a metal layer on a top surface and a sidewall of the copper pillar, and electroplating a metal cap above the top surface of the copper pillar in direct contact with the metal layer. The method further including forming an intermetallic by heating the metal layer and the copper pillar in a non-reducing environment, the intermetallic including elements of both the copper pillar and the metal layer, where molten solder will wet to the metal cap and will not wet to the intermetallic.

Abstract translation: 一种包括形成铜柱的方法，在铜柱的顶表面和侧壁上电镀金属层，并且在铜柱的顶表面上方与金属层直接接触地电镀金属帽。 该方法还包括通过在非还原环境中加热金属层和铜柱形成金属间化合物，金属间化合物包括铜柱和金属层的元素，其中熔融的焊料将润湿金属帽并且不会湿润 到金属间化合物。

公开(公告)号：US20150357235A1

公开(公告)日：2015-12-10

申请号：US14828608

申请日：2015-08-18

Applicant: International Business Machines Corporation ,  SUSS MicroTec Photonic Systems Inc.

Inventor： Yuri M. Brovman ,  Brian M. Erwin ,  Nicholas A. Polomoff ,  Jennifer D. Schuler ,  Matthew E. Souter ,  Christopher L. Tessler

IPC: H01L21/768

CPC classification number: H01L21/76841 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03614 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

公开(公告)号：US20150333025A1

公开(公告)日：2015-11-19

申请号：US14277832

申请日：2014-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Thomas A. Wassick

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/13017 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/1369 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes.

Abstract translation: 本发明一般而且更具体地涉及制造具有不可润湿侧壁的柱状互连结构的方法以及所得到的结构。 更具体地说，本发明可以包括将柱的侧壁仅暴露于与柱的金属反应的有机材料，以在柱的侧壁上形成有机金属层。 在随后的接合/回流工艺期间，有机金属层可以防止焊料在柱的侧壁上润湿。

公开(公告)号：US20200209308A1

公开(公告)日：2020-07-02

申请号：US16816841

申请日：2020-03-12

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  David M. Audette ,  Dennis R. Conti ,  Brian M. Erwin ,  Grant Wagner

IPC: G01R31/28 ,  G01R1/067 ,  B23K26/26

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

公开(公告)号：US10670653B2

公开(公告)日：2020-06-02

申请号：US15979853

申请日：2018-05-15

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  David M. Audette ,  Dennis R. Conti ,  Brian M. Erwin ,  Grant Wagner

IPC: G01R31/28 ,  B23K26/26 ,  G01R1/067

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

公开(公告)号：US10515929B2

公开(公告)日：2019-12-24

申请号：US15948023

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L25/065 ,  H01L23/522 ,  H01L23/13 ,  H01L25/00 ,  H01L23/538

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20190353702A1

公开(公告)日：2019-11-21

申请号：US15979853

申请日：2018-05-15

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  David M. Audette ,  Dennis R. Conti ,  Brian M. Erwin ,  Grant Wagner

IPC: G01R31/28 ,  G01R1/067 ,  B23K26/26

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.