公开(公告)号：US11009545B2

公开(公告)日：2021-05-18

申请号：US16816841

申请日：2020-03-12

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  David M. Audette ,  Dennis R. Conti ,  Brian M. Erwin ,  Grant Wagner

IPC: G01R31/28 ,  B23K26/26 ,  G01R1/067

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

公开(公告)号：US20190148283A1

公开(公告)日：2019-05-16

申请号：US16248013

申请日：2019-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Brian W. Quinlan

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

公开(公告)号：US20180076160A1

公开(公告)日：2018-03-15

申请号：US15813311

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Brian M. Erwin ,  Brittany L. Hedrick ,  Nicholas A. Polomoff ,  TaeHo Kim ,  Matthew E. Souter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11632 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13686 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/053

Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

公开(公告)号：US20170171964A1

公开(公告)日：2017-06-15

申请号：US15271800

申请日：2016-09-21

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/28 ,  H05K3/40 ,  H05K1/03 ,  H05K1/09 ,  H05K3/06

CPC classification number: H05K1/0275 ,  B05D3/102 ,  B41N1/083 ,  C23C22/66 ,  C23C22/76 ,  C23C22/78 ,  C25D11/04 ,  C25D11/045 ,  C25D11/16 ,  H01L23/57 ,  H05K1/00 ,  H05K1/0306 ,  H05K1/0393 ,  H05K1/09 ,  H05K1/115 ,  H05K1/16 ,  H05K3/06 ,  H05K3/28 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/07 ,  H05K2201/09681 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/033 ,  H05K2203/0369 ,  H05K2203/0392 ,  H05K2203/0733 ,  H05K2203/1142

Abstract: A method of making a security mesh comprises forming on a conductive substrate an alumina film having through-holes in which metal, e.g., copper, through-wires are formed. First surface wires are formed on one surface of the alumina film and second surface wires are formed on the second, opposite surface of the alumina film in order to connect selected through-wires into a continuous undulating electrical circuit embedded within the alumina film. The security mesh product comprises an alumina film having a continuous undulating electrical circuit comprising copper or other conductive metal extending therethrough. A stacked security mesh comprises two or more of the mesh products being stacked one above the other.

公开(公告)号：US09431359B2

公开(公告)日：2016-08-30

申请号：US13962194

申请日：2013-08-08

Applicant: International Business Machines Corporation

Inventor： Brian M. Erwin ,  Ian Melville ,  Ekta Misra ,  George J. Scott

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/03848 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13111 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2224/11912 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.

公开(公告)号：US09401336B2

公开(公告)日：2016-07-26

申请号：US14532764

申请日：2014-11-04

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Harry D. Cox ,  Brian M. Erwin ,  Sarah H. Knickerbocker ,  Karen P. McLaughlin ,  David J. Russell

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/03912 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/381 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/1146

Abstract: A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer.

Abstract translation: 半导体结构包括利用多材料沟槽层制造的接触。 多材料沟槽层用于形成接触沟槽，并且接触沟槽用于在其中形成接触。 沟槽层包括下阻挡沟槽层和上光电处理层。 光刻处理层采用图案形成接触沟槽。 阻挡层保护用于形成接触的电镀导电层免受在去除光处理层期间可能发生的腐蚀。

公开(公告)号：US09190376B1

公开(公告)日：2015-11-17

申请号：US14277832

申请日：2014-05-15

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Thomas A. Wassick

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/13017 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/1369 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes.

Abstract translation: 本发明一般而且更具体地涉及制造具有不可润湿侧壁的柱状互连结构的方法以及所得到的结构。 更具体地说，本发明可以包括将柱的侧壁仅暴露于与柱的金属反应的有机材料，以在柱的侧壁上形成有机金属层。 在随后的接合/回流工艺期间，有机金属层可以防止焊料在柱的侧壁上润湿。

公开(公告)号：US20150311161A1

公开(公告)日：2015-10-29

申请号：US14263423

申请日：2014-04-28

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Harry D. Cox ,  Brian M. Erwin ,  John J. Garant ,  Ekta Misra ,  Nicholas A. Polomoff ,  Jennifer D. Schuler

IPC: H01L23/532 ,  H01L21/321 ,  H01L21/288 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  C25D3/38 ,  C25D5/02 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a stack of layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers comprising a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another, removing a first portion of the fourth layer outside the opening to expose a portion of the third layer, a second portion of the fourth layer remains within the opening, filling the opening with a metal by applying an electrical potential to the second layer during an electroplating technique in which the metal plates out on the fourth layer but does not plate out on the third layer, and removing portions of the first layer, the second layer, and the third layer to expose an upper surface of the dielectric layer between the opening and an adjacent opening.

Abstract translation: 一种方法，包括在电介质层的顶部和电介质层的开口内形成层叠层，所述层叠层包括第一层，第二层，第三层和第四层， 另一个顶部，除去开口外部的第四层的第一部分以暴露第三层的一部分，第四层的第二部分保留在开口内，通过向第二层施加电势而用金属填充开口 在电镀技术中，金属板在第四层上排出但不在第三层上沉积，并且去除第一层，第二层和第三层的部分以暴露介电层的上表面 在开口和相邻开口之间。

公开(公告)号：US10892249B2

公开(公告)日：2021-01-12

申请号：US16427631

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20190312011A1

公开(公告)日：2019-10-10

申请号：US16427631

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/13

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.