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公开(公告)号:US10886186B2
公开(公告)日:2021-01-05
申请号:US16365837
申请日:2019-03-27
发明人: Thorsten Scharf , Ralf Otremba , Thomas Bemmerl , Irmgard Escher-Poeppel , Martin Gruber , Michael Juerss , Thorsten Meyer , Xaver Schloegel
IPC分类号: H01L23/053 , H01L23/08 , H01L23/00 , H01L23/40
摘要: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.
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公开(公告)号:US20200352034A1
公开(公告)日:2020-11-05
申请号:US16932925
申请日:2020-07-20
发明人: Thomas Bemmerl , Joachim Mahler
IPC分类号: H05K3/32 , H01L23/488 , B22F7/08 , B22F7/06 , H05K7/02
摘要: A method includes providing a joining material between a surface of a component and a surface of an electronic component. A plurality of spacer elements is embedded in the joining material. The spacer elements are coated with a coating material. The coating material includes sinter particles. A dimension of the sinter particles is greater than 1 nanometer and smaller than 1000 nanometers. The method further includes forming interconnects from the coating material. The interconnects are arranged between the spacer elements and the surface of the component, and between the spacer elements and the surface of the electronic component.
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公开(公告)号:US20200168575A1
公开(公告)日:2020-05-28
申请号:US16695866
申请日:2019-11-26
发明人: Thomas Bemmerl , Chooi Mei Chong , Edward Myers , Michael Stadler
IPC分类号: H01L23/00
摘要: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.
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公开(公告)号:US20200152554A1
公开(公告)日:2020-05-14
申请号:US16678000
申请日:2019-11-08
发明人: Michael Stadler , Thomas Bemmerl
IPC分类号: H01L23/495 , H01L23/31 , H01L23/00 , H01L21/48
摘要: A clip, a semiconductor package, and a method are disclosed. In one example the clip includes a die attach portion having a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and including a curved transition from an inner wall of the at least one through-hole to the first main face.
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公开(公告)号:US20150145109A1
公开(公告)日:2015-05-28
申请号:US14091545
申请日:2013-11-27
发明人: Thomas Bemmerl
IPC分类号: H01L23/498 , H01L23/495
CPC分类号: H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L2224/48091 , H01L2224/48247 , H01L2924/181 , H01L2924/1815 , H01L2924/00014 , H01L2924/00012
摘要: A semiconductor package includes a housing having a bottom surface and an upper surface and a solder pad arranged in the bottom surface of the housing. The solder pad includes a solderable through hole. The housing includes an opening extending from the through hole to the upper surface of the housing.
摘要翻译: 半导体封装包括具有底表面和上表面的壳体和布置在壳体的底表面中的焊盘。 焊盘包括可焊接通孔。 壳体包括从通孔延伸到壳体的上表面的开口。
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公开(公告)号:US20150064844A1
公开(公告)日:2015-03-05
申请号:US14543557
申请日:2014-11-17
发明人: Joachim Mahler , Thomas Bemmerl , Anton Prueckl
IPC分类号: H01L21/768 , H01L25/00
CPC分类号: H01L21/76877 , H01L21/76816 , H01L23/13 , H01L23/3107 , H01L23/4334 , H01L23/49513 , H01L23/49517 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/072 , H01L25/50 , H01L2224/04026 , H01L2224/04034 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/224 , H01L2224/24011 , H01L2224/2402 , H01L2224/24105 , H01L2224/24155 , H01L2224/24175 , H01L2224/244 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/2919 , H01L2224/29294 , H01L2224/29311 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/32225 , H01L2224/32245 , H01L2224/35 , H01L2224/352 , H01L2224/3701 , H01L2224/37113 , H01L2224/37118 , H01L2224/37139 , H01L2224/37144 , H01L2224/37147 , H01L2224/37155 , H01L2224/3716 , H01L2224/37164 , H01L2224/37169 , H01L2224/40095 , H01L2224/40155 , H01L2224/40175 , H01L2224/40245 , H01L2224/40499 , H01L2224/41171 , H01L2224/48155 , H01L2224/48175 , H01L2224/49171 , H01L2224/73263 , H01L2224/73265 , H01L2224/73267 , H01L2224/82104 , H01L2224/82105 , H01L2224/82106 , H01L2224/83447 , H01L2224/83801 , H01L2224/8385 , H01L2224/83851 , H01L2224/84447 , H01L2224/92244 , H01L2224/92246 , H01L2224/92247 , H01L2924/00014 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2924/0105 , H01L2924/01049 , H01L2924/01014 , H01L2924/07811 , H01L2924/01028 , H01L2924/00012 , H01L2924/01023 , H01L2224/45099
摘要: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.
摘要翻译: 电子设备包括与第一芯片载体隔离的第一芯片载体和第二芯片载体。 第一功率半导体芯片安装在电连接到第一芯片载体上。 第二功率半导体芯片安装在第二芯片载体上并电连接到第二芯片载体。 电绝缘材料被配置为至少部分地围绕第一功率半导体芯片和第二功率半导体芯片。 电互连被配置为将第一功率半导体芯片电连接到第二功率半导体芯片,其中电互连具有接触夹和电沉积导体中的至少一个。
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