公开(公告)号：US20230197637A1

公开(公告)日：2023-06-22

申请号：US17554471

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mohammad Enamul Kabir ,  Nitin Deshpande ,  Omkar Karhade ,  Arnab Sarkar ,  Sairam Agraharam ,  Christopher Pelto ,  Gwang-Soo Kim ,  Ravindranath Mahajan

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L23/564 ,  H01L25/0655 ,  H01L21/447

Abstract: Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

公开(公告)号：US20230197546A1

公开(公告)日：2023-06-22

申请号：US17557925

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Sairam Agraharam ,  Nitin Deshpande

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L21/56 ,  H01L2224/32145 ,  H01L2225/06517

Abstract: Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

公开(公告)号：US11574851B2

公开(公告)日：2023-02-07

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US11545407B2

公开(公告)日：2023-01-03

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, Jr.

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US09685421B2

公开(公告)日：2017-06-20

申请号：US14727205

申请日：2015-06-01

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Ravindranath V Mahajan ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/13 ,  H01L21/683 ,  H01L21/677 ,  H01L21/56 ,  H01L23/15

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67709 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/15 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2221/68309 ,  H01L2221/68313 ,  H01L2221/68331 ,  H01L2221/68363 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/8312 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.

公开(公告)号：US20160095220A1

公开(公告)日：2016-03-31

申请号：US14496560

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Nachiket Raravikar

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/28 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/305 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K2201/10734 ,  H05K2203/0191 ,  Y02P70/613 ,  H01L2924/00

Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.

Abstract translation: 一些示例形式涉及电子包装。 电子封装包括电子部件和包括正面和背面的基板。 电子部件安装在基板的前侧，导体安装在基板的背面。 由于电子部件和基板之间的热膨胀系数的差异，基板翘曲。 粘合剂位于基板背侧的导体之​​间，并且粘合剂膜附着到位于基板背面的导体之间的粘合剂。

公开(公告)号：US12061371B2

公开(公告)日：2024-08-13

申请号：US17131621

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Nitin Deshpande ,  Omkar Karhade ,  Ravindranath V. Mahajan

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/367 ,  H01L25/16

CPC classification number: G02B6/4292 ,  G02B6/423 ,  G02B6/4243 ,  G02B6/4268 ,  H01L23/3675 ,  H01L24/16 ,  H01L25/167 ,  H01L2224/16145

Abstract: A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.

公开(公告)号：US20230387074A1

公开(公告)日：2023-11-30

申请号：US17825350

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Nitin Deshpande ,  Satish Damaraju ,  Scott Siers ,  Kai-Chiang Wu

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/16 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2225/06513

Abstract: An integrated circuit assembly may be formed having a first level structure that comprises a monolithic substrate with a first reticle zone including integrated circuitry and a second reticle zone including integrated circuitry, and a second level structure comprising at least one integrated circuit device electrically attached to the integrated circuitry of the first reticle zone of the first level structure and a bridge electrically attaching the integrated circuitry of the first reticle zone of the first level structure and the integrated circuitry of the second reticle zone of the first level structure.

公开(公告)号：US20230197551A1

公开(公告)日：2023-06-22

申请号：US17558294

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/3178 ,  H01L23/293 ,  H01L21/561 ,  H01L25/0652 ,  H01L25/0655 ,  H01L24/08 ,  H01L2224/08145

Abstract: Techniques and mechanisms for a reconstituted circuit device to be formed using a flow of material, by capillary action, in a region between a first die and a second die. In an embodiment, a rigid mass extends around, and between, the first die and the second die. The rigid mass comprises a first body of a first material, and a second body of second material, wherein the bodies each extend across the region to respective sidewall structures of the first and second dies. In the region, a portion of the first body forms a surface structure which adjoins the second body. A concave or convex shape of the surface structure is an artefact of a meniscus formed by the first material during a liquid state thereof. In another embodiment, the reconstituted circuit device further comprises an interconnect which adjoins, and extends through, the rigid mass.

公开(公告)号：US11676900B2

公开(公告)日：2023-06-13

申请号：US15778398

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Nitin Deshpande ,  Shawna M. Liff ,  Omkar Karhade ,  Amram Eitan ,  Timothy A. Gosselin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/36 ,  H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/13 ,  H01L23/36 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/50 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.