中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

32 records (took 0.018 seconds)

    Divider-less fractional PLL architecture
    21.
    发明授权
    Divider-less fractional PLL architecture 有权

    公开(公告)号：US10659061B2

    公开(公告)日：2020-05-19

    申请号：US16472835

    申请日：2016-12-27

    Applicant: Intel Corporation

    Inventor： Elias Nassar ,  Eyal Fayneh ,  Inbar Falkov ,  Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Samer Nassar

    IPC: H03D3/24 ,  H03L7/091 ,  H03L7/099

    Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

    DIVIDER-LESS FRACTIONAL PLL ARCHITECTURE
    22.
    发明申请
    DIVIDER-LESS FRACTIONAL PLL ARCHITECTURE 审中-公开

    公开(公告)号：US20190334533A1

    公开(公告)日：2019-10-31

    申请号：US16472835

    申请日：2016-12-27

    Applicant: Intel Corporation

    Inventor： Elias Nassar ,  Eyal Fayneh ,  Inbar Falkov ,  Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Samer Nassar

    IPC: H03L7/091 ,  H03L7/099

    Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

    Binary stochastic time-to-digital converter and method
    23.
    发明授权
    Binary stochastic time-to-digital converter and method 有权

    公开(公告)号：US09927775B1

    公开(公告)日：2018-03-27

    申请号：US15477057

    申请日：2017-04-01

    Applicant: Intel Corporation

    Inventor： Rotem Banin ,  Assaf Ben-Bassat ,  Evgeny Shumaker ,  Ofir Degani

    IPC: H03M1/50 ,  G04F10/00 ,  H03M1/04 ,  H03K3/037 ,  H03K19/23

    CPC classification number: G04F10/005 ,  H03K19/23

    Abstract: A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.

    VOLTAGE-CONTROLLED OSCILLATOR WITH REDUCED SINGLE-ENDED CAPACITANCE
    24.
    发明申请
    VOLTAGE-CONTROLLED OSCILLATOR WITH REDUCED SINGLE-ENDED CAPACITANCE 审中-公开
    具有降低单端电容的电压控制振荡器

    公开(公告)号：US20150372643A1

    公开(公告)日：2015-12-24

    申请号：US14754108

    申请日：2015-06-29

    Applicant: Intel Corporation

    Inventor： Ori Ashckenazi ,  Rotem Banin ,  Ofir Degani

    IPC: H03B5/12

    CPC classification number: H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1296

    Abstract: Embodiments provide a voltage controlled oscillator (VCO) having reduced single-ended capacitance. In one embodiment, the VCO may include a transformer, a capacitor bank, and a gain stage. The transformer may include a primary inductor and a secondary inductor, and the secondary inductor may be inductively coupled to the primary inductor. The capacitor bank may be coupled to the secondary inductor and may provide a majority of a total capacitance of the VCO. The gain stage may be coupled to the primary inductor and configured to receive a supply signal and to drive a differential current in the primary inductor, thereby inducing an output signal across the secondary inductor having a frequency equal to a resonant frequency of the VCO.

    Abstract translation: 实施例提供具有减小的单端电容的压控振荡器（VCO）。 在一个实施例中，VCO可以包括变压器，电容器组和增益级。 变压器可以包括初级电感器和次级电感器，并且次级电感器可以感应耦合到初级电感器。 电容器组可以耦合到次级电感器并且可以提供VCO的总电容的大部分。 增益级可以耦合到主电感器并且被配置为接收电源信号并驱动初级电感器中的差分电流，从而在频率等于VCO的谐振频率的次级电感器两端产生输出信号。

    Digitally controlled edge interpolator (DCEI) for digital to time converters (DTC)
    25.
    发明授权
    Digitally controlled edge interpolator (DCEI) for digital to time converters (DTC) 有权
    用于数字到时间转换器（DTC）的数字控制边缘内插器（DCEI）

    公开(公告)号：US09137084B2

    公开(公告)日：2015-09-15

    申请号：US13958295

    申请日：2013-08-02

    Applicant: Intel Corporation

    Inventor： Ofir Degani ,  Rotem Banin ,  Ashoke Ravi

    IPC: H04L27/36 ,  H03F1/02 ,  H03F3/217 ,  H03F3/24

    CPC classification number: H04L27/36 ,  H03F1/0216 ,  H03F3/2175 ,  H03F3/245

    Abstract: A Digital-to-Time (DTC) for a Digital Polar Transmitter (DPT) comprises a coarse delay/phase segment and a fine delay/phase segment. The coarse delay/phase segment generates an even delay/phase signal and an odd delay/phase signal. The fine/phase delay segment receives the even coarse phase signal and the odd coarse phase signal, and is responsive to a fine delay/phase control signal to generate a fine delay/phase output signal that is an interpolation of the even delay/phase signal and the odd delay/phase signal. In one exemplary embodiment, the fine delay/phase control signal comprises a binary signal having 2N values, and the fine delay/phase segment comprises 2N interpolators. Each interpolator is coupled to the even and odd coarse phase signals and is controlled by the fine delay/phase control signal to be responsive to the even coarse phase signal or the odd coarse phase signal based on a value of the fine delay/phase control signal.

    Abstract translation: 用于数字极性发射器（DPT）的数字时间（DTC）包括粗延迟/相位段和精细延迟/相位段。 粗延迟/相位段产生均匀的延迟/相位信号和奇数延迟/相位信号。 精细/相位延迟段接收均匀粗略相位信号和奇数粗略相位信号，并且响应于精细延迟/相位控制信号以产生精细延迟/相位输出信号，其是偶数延迟/相位信号的内插 和奇延迟/相位信号。 在一个示例性实施例中，精细延迟/相位控制信号包括具有2N个值的二进制信号，并且精细延迟/相位段包括2N个内插器。 每个内插器耦合到偶数和奇数粗略相位信号，并由细微延迟/相位控制信号控制，以响应于均匀粗略相位信号或奇数粗略相位信号，基于精细延迟/相位控制信号的值 。

Patent Agency Ranking