公开(公告)号：US20100314759A1

公开(公告)日：2010-12-16

申请号：US12862053

申请日：2010-08-24

申请人： Roden R. Topacio

发明人： Roden R. Topacio

IPC分类号： H01L23/488

CPC分类号： H01L24/03 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14

摘要： Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads.

摘要翻译： 公开了各种半导体芯片钝化结构及其制造方法。 一方面，提供一种制造方法，其包括将聚合物钝化层施加到半导体芯片的一侧。 半导体芯片的一侧包括多个导体焊盘。 在聚合物钝化层中形成多个开口以露出多个导体焊盘。 在多个导体焊盘上形成多个导体结构。

公开(公告)号：US20100155938A1

公开(公告)日：2010-06-24

申请号：US12339759

申请日：2008-12-19

申请人： Liane Martinez ,  Roden R. Topacio ,  Yip Seng Low

发明人： Liane Martinez ,  Roden R. Topacio ,  Yip Seng Low

IPC分类号： H01L23/498 ,  H01L21/60 ,  G06F19/00

CPC分类号： G06F17/5068 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/85181 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/92127 ,  H01L2224/92163 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2224/11 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

摘要翻译： 集成电路（IC）产品包括具有至少一个导电层的再分配层（RDL），该导电层被配置为将电信息从一个位置分配到IC中的另一个位置。 RDL还包括多个引线接合焊盘和多个焊盘。 多个焊盘各自包括与RDL直接电连通的焊料可润湿材料。

公开(公告)号：US20120261812A1

公开(公告)日：2012-10-18

申请号：US13086672

申请日：2011-04-14

申请人： Roden R. Topacio

发明人： Roden R. Topacio

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03902 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05019 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/81805

摘要： Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes providing a semiconductor chip that has a conductor pad and a passivation structure over the conductor pad. A first metallic layer is applied on the passivation structure and in electrical contact with the conductor pad. The first metallic layer covers a first portion but not a second portion of the passivation structure. A second metallic layer is applied to the first metallic layer. A polymer layer is applied to the second metallic layer. The polymer layer includes a first opening in alignment with the first metallic layer that exposes a portion of the second layer. A conducting solder barrier layer is applied to the exposed portion of the second metallic layer.

摘要翻译： 公开了各种半导体芯片焊料凸块和底部金属化（UBM）结构及其制造方法。 在一个方面，提供了一种方法，其包括提供在导体焊盘上具有导体焊盘和钝化结构的半导体芯片。 第一金属层施加在钝化结构上并与导体焊盘电接触。 第一金属层覆盖钝化结构的第一部分而不是第二部分。 将第二金属层施加到第一金属层。 将聚合物层施加到第二金属层。 聚合物层包括与暴露第二层的一部分的第一金属层对准的第一开口。 导电焊料阻挡层被施加到第二金属层的暴露部分。

公开(公告)号：US07973408B2

公开(公告)日：2011-07-05

申请号：US12862053

申请日：2010-08-24

申请人： Roden R. Topacio

发明人： Roden R. Topacio

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/03 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14

摘要： Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads.

摘要翻译： 公开了各种半导体芯片钝化结构及其制造方法。 一方面，提供一种制造方法，其包括将聚合物钝化层施加到半导体芯片的一侧。 半导体芯片的一侧包括多个导体焊盘。 在聚合物钝化层中形成多个开口以露出多个导体焊盘。 在多个导体焊盘上形成多个导体结构。

公开(公告)号：US20110057307A1

公开(公告)日：2011-03-10

申请号：US12557336

申请日：2009-09-10

申请人： Roden R. Topacio ,  Yip Seng Low

发明人： Roden R. Topacio ,  Yip Seng Low

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49838 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/05624 ,  H01L2924/01039 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads.

摘要翻译： 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供一种制造方法，其包括在半导体芯片的第一侧上形成第一导体结构，并形成与第一导体结构电接触的第二导体结构。 第二导体结构适于耦合到焊料结构并且包括具有至少两个胎面的楼梯布置。

公开(公告)号：US07888259B2

公开(公告)日：2011-02-15

申请号：US12194265

申请日：2008-08-19

申请人： Adam R. Zbrzezny ,  Roden R. Topacio

发明人： Adam R. Zbrzezny ,  Roden R. Topacio

IPC分类号： H01L21/00

CPC分类号： H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/02 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H05K3/3457 ,  H05K2201/0373 ,  Y02P70/611

摘要： An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described.

摘要翻译： 集成电路封装采用包括适于接收焊料的预定三维表面的焊盘。 在一个示例中，预定的三维表面包括至少一个预定的山丘或突出部分和在山丘部分和谷部之间具有预定相对高度的诸如下部分的谷部分。 预定的三维表面可以以任何合适的配置进行配置，并且可以包括轮廓图案，非图案或任何其它合适的配置。 还描述了相关方法。

公开(公告)号：US20100044884A1

公开(公告)日：2010-02-25

申请号：US12194265

申请日：2008-08-19

申请人： Adam R. Zbrzezny ,  Roden R. Topacio

发明人： Adam R. Zbrzezny ,  Roden R. Topacio

IPC分类号： H01L21/768 ,  H01L23/492

CPC分类号： H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/02 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H05K3/3457 ,  H05K2201/0373 ,  Y02P70/611

摘要： An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described.

摘要翻译： 集成电路封装采用包括适于接收焊料的预定三维表面的焊盘。 在一个示例中，预定的三维表面包括至少一个预定的山丘或突出部分和在山丘部分和谷部之间具有预定相对高度的诸如下部分的谷部分。 预定的三维表面可以以任何合适的配置进行配置，并且可以包括轮廓图案，非图案或任何其它合适的配置。 还描述了相关方法。

公开(公告)号：US20090278264A1

公开(公告)日：2009-11-12

申请号：US12119174

申请日：2008-05-12

申请人： Roden R. Topacio ,  Vincent Chan ,  Fan Yeung

发明人： Roden R. Topacio ,  Vincent Chan ,  Fan Yeung

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H05K3/3452 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H05K2201/0989 ,  H05K2201/10674 ,  H01L2924/00014

摘要： Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.

摘要翻译： 公开了各种半导体芯片封装及其制造方法。 在一个方面，提供了一种制造方法，其包括将焊料凸点耦合到半导体芯片的一侧，并使焊料凸块与耦合到基板的导体焊盘接触并定位在衬底上的焊料掩模的开口中 。 导体垫具有第一横向尺寸，并且开口具有大于第一横向尺寸的第二横向尺寸。 在焊料凸块和导体焊盘之间建立冶金结合。

公开(公告)号：US10403589B2

公开(公告)日：2019-09-03

申请号：US15639812

申请日：2017-06-30

申请人： Roden R. Topacio

发明人： Roden R. Topacio

IPC分类号： H01L21/311 ,  H01L23/00 ,  H01L21/78

摘要： Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.

公开(公告)号：US20170301638A1

公开(公告)日：2017-10-19

申请号：US15639812

申请日：2017-06-30

申请人： Roden R. Topacio

发明人： Roden R. Topacio

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/311

CPC分类号： H01L24/11 ,  H01L21/31144 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1146 ,  H01L2224/119 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/014

摘要： Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.