公开(公告)号：US09607935B2

公开(公告)日：2017-03-28

申请号：US12427133

申请日：2009-04-21

申请人： Liane Martinez ,  Neil McLellan ,  Silqun Leung ,  Gabriel Wong

发明人： Liane Martinez ,  Neil McLellan ,  Silqun Leung ,  Gabriel Wong

IPC分类号： H05K7/00 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34

CPC分类号： H01L23/49816 ,  H01L23/50 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/0562 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/145 ,  H05K3/3442 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/00014

摘要： Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a first side of a carrier substrate where the carrier substrate includes a second side opposite the first side. At least one passive device is coupled to the second side of the carrier substrate. The at least one passive device includes at least one first terminal electrically coupled to the semiconductor chip and at least one second terminal adapted to couple to a printed circuit board.

公开(公告)号：US20100155938A1

公开(公告)日：2010-06-24

申请号：US12339759

申请日：2008-12-19

申请人： Liane Martinez ,  Roden R. Topacio ,  Yip Seng Low

发明人： Liane Martinez ,  Roden R. Topacio ,  Yip Seng Low

IPC分类号： H01L23/498 ,  H01L21/60 ,  G06F19/00

CPC分类号： G06F17/5068 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/85181 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/92127 ,  H01L2224/92163 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2224/11 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

摘要翻译： 集成电路（IC）产品包括具有至少一个导电层的再分配层（RDL），该导电层被配置为将电信息从一个位置分配到IC中的另一个位置。 RDL还包括多个引线接合焊盘和多个焊盘。 多个焊盘各自包括与RDL直接电连通的焊料可润湿材料。

公开(公告)号：US20130147026A1

公开(公告)日：2013-06-13

申请号：US13323177

申请日：2011-12-12

申请人： Roden R. TOPACIO ,  Liane Martinez ,  Yip Seng Low

发明人： Roden R. TOPACIO ,  Liane Martinez ,  Yip Seng Low

IPC分类号： H01L23/36 ,  H01L23/48

CPC分类号： H01L23/36 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2924/00

摘要： According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.

摘要翻译： 根据一个实施例，一种用于封装封装器件的顶部封装和底部封装之间的封装封装式散热器插入器可以包括位于顶部封装之下的顶部散热器; 位于顶部散热片下方的插入器基板; 位于插入器底部下方的底部散热器; 在所述插入器基板和所述顶部散热器之间的第一内插基板金属层; 在所述插入器基板和所述底部散热器之间的第二插入件基板金属层; 以及在第二插入器基板金属层和底部封装之间的插入件焊球。

公开(公告)号：US07847568B2

公开(公告)日：2010-12-07

申请号：US11840587

申请日：2007-08-17

申请人： Andrew Gangoso ,  Liane Martinez

发明人： Andrew Gangoso ,  Liane Martinez

IPC分类号： G01R31/02

CPC分类号： G01R1/07314 ,  G01R31/2846 ,  G01R31/2887 ,  Y10T29/49117

摘要： Various probe substrates for probing a semiconductor die and methods of use thereof are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first matrix array of conductor pins and a second matrix array of conductor pins on a probe substrate. The second matrix array of conductor pins is separated from the first matrix array of conductor pins by a first pitch along a first axis selected to substantially match a second pitch between a first semiconductor die and a second semiconductor die of a semiconductor workpiece.

摘要翻译： 公开了用于探测半导体管芯的各种探针衬底及其使用方法。 一方面，提供一种制造方法，其包括在探针基板上形成导体引脚的第一矩阵阵列和导体引脚的第二矩阵阵列。 导体引脚的第二矩阵阵列沿着第一轴线与导体引脚的第一矩阵阵列分离，所述第一轴线被选择为基本匹配半导体工件的第一半导体管芯和第二半导体管芯之间的第二间距。

公开(公告)号：US09209106B2

公开(公告)日：2015-12-08

申请号：US13529720

申请日：2012-06-21

申请人： Xiao Ling Shi ,  Suming Hu ,  Liane Martinez ,  Roden Topacio ,  Terence Cheung

发明人： Xiao Ling Shi ,  Suming Hu ,  Liane Martinez ,  Roden Topacio ,  Terence Cheung

IPC分类号： H05K7/20 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K3/34

CPC分类号： H01L23/3677 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/0206 ,  H05K3/3436 ,  H05K2201/10416 ,  Y10T29/49139

摘要： A method of assembling a semiconductor chip device is provided. The method includes providing a first circuit board that has a plurality of thermally conductive vias. A second circuit board is mounted on the first circuit board over and in thermal contact with the thermally conductive vias. The second circuit board includes first side facing the first circuit board and a second and opposite side.

摘要翻译： 提供了组装半导体芯片器件的方法。 该方法包括提供具有多个导热通孔的第一电路板。 第二电路板安装在第一电路板上并与导热通孔热接触。 第二电路板包括面向第一电路板的第一面和第二相对侧。

公开(公告)号：US20110225813A1

公开(公告)日：2011-09-22

申请号：US13152918

申请日：2011-06-03

申请人： Andrew Leung ,  Roden Topacio ,  Liane Martinez ,  Yip Seng Low

发明人： Andrew Leung ,  Roden Topacio ,  Liane Martinez ,  Yip Seng Low

IPC分类号： H01R43/00

CPC分类号： H01L23/49822 ,  B32B37/02 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/00 ,  H01L21/4857 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09136 ,  Y10T29/49117 ,  Y10T156/10 ,  H01L2224/05599

摘要： A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m≠n is disclosed. The method includes forming (m−n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials.

摘要翻译： 制造用于具有芯的电子封装的基板的制造方法，其中m≠n公开在芯的第一表面上的m累积层和在芯的第二表面上的n累积层。 该方法包括在第一表面上形成m个聚集层（m-n），然后形成n对堆积层，其中每一对包括形成在第二表面上的n个积聚层中的一个， 在第一表面上形成的m个积聚层的剩余n。 每个堆积层包括介电层和形成在其上的导电层。 所公开的方法通过避免电介质材料的重复去除，来保护每个构建层中的电介质层在衬底制造过程中不被超量化。

公开(公告)号：US20090152690A1

公开(公告)日：2009-06-18

申请号：US11956434

申请日：2007-12-14

申请人： Yue Li ,  Silqun Leung ,  Terence Cheung ,  Sally Yeung ,  Liane Martinez

发明人： Yue Li ,  Silqun Leung ,  Terence Cheung ,  Sally Yeung ,  Liane Martinez

IPC分类号： H01L23/48 ,  H01L21/58

CPC分类号： H01L23/50 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/19105 ,  H05K1/0295 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09663 ,  H05K2201/099 ,  H05K2201/09954 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

摘要： Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings that expose selected portions of the plural conductor pads. Each of the plural openings has a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate. A conductor material is placed in the plural openings to establish plural capacitor pads.

摘要翻译： 公开了用于将电容器耦合到芯片衬底的各种方法和装置。 一方面，提供一种制造方法，其包括在具有多个导体焊盘的半导体芯片基板上形成掩模。 该掩模具有多个露出多个导体焊盘的选定部分的开口。 多个开口中的每一个具有对应于适于耦合到半导体芯片衬底的电容器的最小尺寸端子的覆盖区的覆盖区。 将导体材料放置在多个开口中以建立多个电容器焊盘。

公开(公告)号：US08637983B2

公开(公告)日：2014-01-28

申请号：US12339759

申请日：2008-12-19

申请人： Liane Martinez ,  Roden R. Topacio ,  Yip Seng Low

发明人： Liane Martinez ,  Roden R. Topacio ,  Yip Seng Low

IPC分类号： H01L23/498 ,  H01L21/60 ,  G06F19/00

CPC分类号： G06F17/5068 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/85181 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/92127 ,  H01L2224/92163 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2224/11 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

摘要翻译： 集成电路（IC）产品包括具有至少一个导电层的再分配层（RDL），该导电层被配置为将电信息从一个位置分配到IC中的另一个位置。 RDL还包括多个引线接合焊盘和多个焊盘。 多个焊盘各自包括与RDL直接电连通的焊料可润湿材料。

公开(公告)号：US08564122B2

公开(公告)日：2013-10-22

申请号：US13316040

申请日：2011-12-09

申请人： Neil R. McLellan ,  Liane Martinez ,  Yip Seng Low ,  Suming Hu

发明人： Neil R. McLellan ,  Liane Martinez ,  Yip Seng Low ,  Suming Hu

IPC分类号： H01L23/10

CPC分类号： H01L23/3675 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/16 ,  H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433 ,  H01L23/467 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83815 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/81805

摘要： Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.

摘要翻译： 公开了各种电路板及其制造方法。 在一个方面，提供了一种制造方法，其包括将电非功能部件耦合到第一电路板的表面。 电非功能部件具有第一高度。 电路板的表面适于安装有半导体芯片。 电功能部件从电气非功能部件向内安装到表面。 电功能部件具有小于第一高度的第二仰角。

公开(公告)号：US20130147012A1

公开(公告)日：2013-06-13

申请号：US13316040

申请日：2011-12-09

申请人： Neil R. McLellan ,  Liane Martinez ,  Yip Seng Low ,  Suming Hu

发明人： Neil R. McLellan ,  Liane Martinez ,  Yip Seng Low ,  Suming Hu

IPC分类号： H01L27/06 ,  H01L21/50

CPC分类号： H01L23/3675 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/16 ,  H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433 ,  H01L23/467 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83815 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/81805

摘要： Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.

摘要翻译： 公开了各种电路板及其制造方法。 在一个方面，提供了一种制造方法，其包括将电非功能部件耦合到第一电路板的表面。 电非功能部件具有第一高度。 电路板的表面适于安装有半导体芯片。 电功能部件从电气非功能部件向内安装到表面。 电功能部件具有小于第一高度的第二仰角。