公开(公告)号：US20180138319A1

公开(公告)日：2018-05-17

申请号：US15349162

申请日：2016-11-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Ali SALIH ,  Gordon M. GRIVNA ,  Daniel R. HEUTTL ,  Osamu ISHIMARU ,  Thomas KEENA ,  Masafumi UEHARA

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/41 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L29/861 ,  H01L27/0814 ,  H01L29/0623 ,  H01L29/0684 ,  H01L29/407 ,  H01L29/41 ,  H01L29/45 ,  H01L29/66136

Abstract: A semiconductor device structure includes a region of semiconductor material with a first major surface and an opposing second major surface. A contact structure is disposed in a first portion of the region of semiconductor material and includes a tub structure extending from adjacent a first portion of the first major surface. A plurality of structures comprising portions of the region of semiconductor material extend outward from a lower surface of the tub structure. In some embodiments, the plurality of structures comprises a plurality of free-standing structures. A conductive material is disposed within the tub structure and laterally surrounding the plurality of structures. In one embodiment, the contact structure facilitates the fabrication of a monolithic series switching diode structure having a low-resistance substrate contact.

公开(公告)号：US20170317072A1

公开(公告)日：2017-11-02

申请号：US15648211

申请日：2017-07-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Zia HOSSAIN ,  Chun-Li LIU ,  Jason MCDONALD ,  Ali SALIH ,  Alexander YOUNG

IPC: H01L27/06 ,  H01L21/8258 ,  H01L23/367 ,  H01L27/02 ,  H01L29/417 ,  H01L21/74 ,  H01L29/10 ,  H01L29/778 ,  H01L29/872 ,  H01L23/48 ,  H01L29/20 ,  H01L29/861

CPC classification number: H01L27/0629 ,  H01L21/743 ,  H01L21/8258 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0688 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7783 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the second current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the first current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.

公开(公告)号：US20160322969A1

公开(公告)日：2016-11-03

申请号：US15133644

申请日：2016-04-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Peter MOENS ,  Mihir MUDHOLKAR ,  Joe FULTON ,  Philip CELAYA ,  Stephen ST. GERMAIN ,  Chun-Li LIU ,  Jason MCDONALD ,  Alexander YOUNG ,  Ali SALIH

IPC: H03K17/687 ,  H01L25/11 ,  H01L29/778

CPC classification number: H01L29/747 ,  H01L21/8258 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/40 ,  H01L25/115 ,  H01L25/18 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/205 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/7416 ,  H01L29/742 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H03K17/6874 ,  H03K2017/6878 ,  H03K2217/0009 ,  H03K2217/0018 ,  H01L2224/37099

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract translation: 半桥电路可以包括高侧HEMT，高侧开关晶体管，低侧HEMT和低侧开关晶体管。 HEMT的管芯衬底可以耦合到其相应的开关晶体管的源极。 在另一方面，用于半桥电路的封装电子器件可以具有可以使用有助于减小寄生电感和电阻的较短连接器的设计。 在另一方面，用于半桥电路的封装电子设备可以包括沿着封装底部的多于一个的连接允许沿着封装的电子器件的周边的较少的引线连接并且可以允许较小的封装。

公开(公告)号：US20160118490A1

公开(公告)日：2016-04-28

申请号：US14853720

申请日：2015-09-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Zia HOSSAIN ,  Chun-Li LIU ,  Jason MCDONALD ,  Ali SALIH ,  Alexander YOUNG

IPC: H01L29/778 ,  H01L27/02

CPC classification number: H01L27/0629 ,  H01L21/743 ,  H01L21/8258 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0688 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7783 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.

Abstract translation: 在一个实施例中，III-V族晶体管结构包括设置在半导体衬底上的异质结构。 第一载流电极和第二载流电极邻近异质结构的主表面设置，并且控制电极设置在第一和第二载流电极之间。 钳位装置与III-V族晶体管结构集成，并且在第一电流承载电极处电连接第三电极，以在例如电应力事件期间提供次级电流路径。

公开(公告)号：US20160099314A1

公开(公告)日：2016-04-07

申请号：US14508266

申请日：2014-10-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kirk HUANG ,  Chun-Li LIU ,  Ali SALIH

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/0696 ,  H01L27/0629 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/78

Abstract: In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value.

Abstract translation: 在一个实施例中，形成MOS晶体管的方法包括：形成MOS晶体管的阈值电压（Vth），以在MOS晶体管的内部具有第一值，并且在远离MOS晶体管的其他位置处形成第二值 所述内部部分，其中所述第二值小于所述第一值。

公开(公告)号：US20160043181A1

公开(公告)日：2016-02-11

申请号：US14741567

申请日：2015-06-17

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li LIU ,  Ali SALIH

IPC: H01L29/20 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/2003 ,  H01L29/1083 ,  H01L29/404 ,  H01L29/42376 ,  H01L29/7783 ,  H01L29/78681 ,  H01L29/78696

Abstract: An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof.

Abstract translation: 电子器件可以具有包括化合物半导体材料的沟道层的晶体管。 在一个实施例中，沟道层覆盖包括载流子阻挡区域和载流子积聚区域的半导体层。 电荷势垒区域可以帮助减少从捕获的载流子从沟道层进入电荷势垒区域的可能性，并且电荷累积区域可以帮助排斥沟道层中的载流子远离电荷阻挡层。 在另一个实施例中，阻挡层覆盖在沟道层上。 本文描述的实施例可以有助于产生较低的动态导通电阻，较低的漏电流，另一有益效果或其任何组合。

公开(公告)号：US20150340482A1

公开(公告)日：2015-11-26

申请号：US14814106

申请日：2015-07-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  John Michael PARSEY, JR. ,  Ali SALIH ,  Prasad VENKATRAMAN

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7783 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/785 ,  H01L29/872

Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.

Abstract translation: 在一个实施例中，III族氮化物材料用于形成半导体器件。 在III族氮化物材料中形成翅片结构，并且栅极结构，源电极和漏电极形成为与翅片结构间隔开的关系。 鳍结构提供极性和半极性2DEG区域。 在一个实施例中，门结构被配置为控制极地2DEG区域中的电流。 屏蔽导体层包括在栅极结构之上并与半导体器件的漏极区间隔开。