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    Fabrication method of semiconductor package
    21.
    发明授权
    Fabrication method of semiconductor package 有权

    公开(公告)号：US10811367B2

    公开(公告)日：2020-10-20

    申请号：US16360511

    申请日：2019-03-21

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538 ,  H01L23/16 ,  H01L23/31 ,  H01L21/768

    Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

    METHOD FOR MANUFACTURING ELECTRONIC PACKAGE
    22.
    发明申请
    METHOD FOR MANUFACTURING ELECTRONIC PACKAGE 审中-公开

    公开(公告)号：US20200258802A1

    公开(公告)日：2020-08-13

    申请号：US16862024

    申请日：2020-04-29

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L23/16

    Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

    SUBSTRATE HAVING ELECTRICAL INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF
    24.
    发明申请
    SUBSTRATE HAVING ELECTRICAL INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF 有权
    具有电气互连结构的基板及其制造方法

    公开(公告)号：US20150303139A1

    公开(公告)日：2015-10-22

    申请号：US14688510

    申请日：2015-04-16

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Po-Yi Wu ,  Chun-Hung Lu

    IPC: H01L23/498 ,  C23F1/00 ,  H01L21/48

    CPC classification number: C23F1/00 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

    Abstract translation: 提供一种制造具有电互连结构的基板的方法，其包括以下步骤：提供具有多个导电焊盘的衬底主体和顺序形成在衬底主体上并暴露导电焊盘的第一和第二钝化层; 在所述第二钝化层和所述导电焊盘上形成晶种层; 在每个所述导电焊盘上形成第一金属层，其中所述第一金属层嵌入所述第一钝化层和所述第二钝化层中，而不会从所述第二钝化层突出; 以及在所述第一金属层上形成从所述第二钝化层突出的第二金属层。 因此，当通过使用蚀刻剂的蚀刻去除第二钝化层上的种子层时，蚀刻剂不会侵蚀第一金属层，从而防止在第二金属层下面形成底切结构。

    Fabrication method of substrate having electrical interconnection structures
    27.
    发明授权
    Fabrication method of substrate having electrical interconnection structures 有权

    公开(公告)号：US10774427B2

    公开(公告)日：2020-09-15

    申请号：US15867919

    申请日：2018-01-11

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Po-Yi Wu ,  Chun-Hung Lu

    IPC: H05K3/40 ,  C23F1/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14

    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

    Fabrication method of semiconductor package
    28.
    发明授权
    Fabrication method of semiconductor package 有权

    公开(公告)号：US10340228B2

    公开(公告)日：2019-07-02

    申请号：US15698136

    申请日：2017-09-07

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

    Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

    FABRICATION METHOD OF SUBSTRATE HAVING ELECTRICAL INTERCONNECTION STRUCTURES
    30.
    发明申请
    FABRICATION METHOD OF SUBSTRATE HAVING ELECTRICAL INTERCONNECTION STRUCTURES 审中-公开

    公开(公告)号：US20180135185A1

    公开(公告)日：2018-05-17

    申请号：US15867919

    申请日：2018-01-11

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Po-Yi Wu ,  Chun-Hung Lu

    IPC: C23F1/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498

    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

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