公开(公告)号：US20160196990A1

公开(公告)日：2016-07-07

申请号：US15074110

申请日：2016-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。

公开(公告)号：US20140252603A1

公开(公告)日：2014-09-11

申请号：US14056230

申请日：2013-10-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Yi-Che Lai ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/1401 ,  H01L2224/1412 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.

Abstract translation: 提供一种半导体器件，包括：具有相对的第一和第二表面的衬底和穿过第一和第二表面的多个导电通孔; 绝缘层，形成在所述基板的所述第一表面上，并暴露所述导电通孔的端部; 以及在导电通孔的端部的周边形成在绝缘层上的缓冲层，从而提高产品的可靠性和良好的产率。

公开(公告)号：US20140080242A1

公开(公告)日：2014-03-20

申请号：US14078845

申请日：2013-11-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-An Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu

IPC: B81C1/00

CPC classification number: H01L29/84 ,  B81B7/007 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high.

Abstract translation: 封装结构包括具有多个电触头的微机电元件; 封装层，其包围微机电元件和电触点，微机电元件的底表面从封装层的下表面露出; 嵌入在所述封装层中的多个接合线，每个所述接合线的一端连接到所述电接触中的一个，另一端从所述封装层的下表面露出; 以及设置在所述封装层的下表面上的堆积层结构，所述堆积层包括至少一个电介质层和形成在所述电介质层中并且电连接到所述接合线的一端的多个导电盲孔 。 封装结构更容易精确地控制外部电触头的位置，并且制造程序的兼容性高。

公开(公告)号：US09899237B2

公开(公告)日：2018-02-20

申请号：US14174988

申请日：2014-02-07

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/673 ,  H01L21/768 ,  H01L21/78 ,  H01L21/68 ,  H01L21/48 ,  H01L21/683 ,  H01L21/677

CPC classification number: H01L21/56 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/673 ,  H01L21/67333 ,  H01L21/67763 ,  H01L21/68 ,  H01L21/683 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

公开(公告)号：US20170229364A1

公开(公告)日：2017-08-10

申请号：US15497964

申请日：2017-04-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

公开(公告)号：US20170148761A1

公开(公告)日：2017-05-25

申请号：US15400608

申请日：2017-01-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

公开(公告)号：US09425119B2

公开(公告)日：2016-08-23

申请号：US14273952

申请日：2014-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Shih-Kuang Chiu

IPC: H01L23/28 ,  H01L21/768 ,  B81B7/00 ,  G01L19/00 ,  G01L19/14 ,  H01L23/10

CPC classification number: H01L23/28 ,  B81B7/0061 ,  B81B7/007 ,  B81B2207/098 ,  G01L19/0076 ,  G01L19/147 ,  H01L23/10 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure.

Abstract translation: 提供了一种封装结构，其包括：具有带有凹槽的表面的晶片，封闭凹槽的开口端的薄膜和电触头; 芯片，其表面具有导电层，与凹部相对的表面和位于凹部周边的密封环，芯片设置在晶片上，密封环围绕薄膜，电触点位于 密封环外; 形成在晶片上用于封装芯片和电触点的密封剂; 多个次级导电线嵌入密封剂中，其一端从密封剂的顶表面露出，另一端与电触点电连接; 以及穿透晶片并与凹部连通的通孔，从而降低了封装结构的制造成本和尺寸。

公开(公告)号：US09117698B2

公开(公告)日：2015-08-25

申请号：US14449278

申请日：2014-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Jung-Pang Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu ,  Guang-Hwa Ma

IPC: H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/50 ,  H01L29/84 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L23/538

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/48227 ,  H01L2224/81 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract translation: 半导体封装包括：具有相反的第一和第二表面的电介质层; 嵌入在介电层中并具有多个电极焊盘的半导体芯片; 分别设置在半导体芯片的电极焊盘上的多个第一金属柱，使得第一金属柱的顶端从第一表面露出; 至少第二金属柱穿透介电层，使得第二金属柱的两个相对端分别从第一表面和第二表面露出; 第一电路层，形成在第一表面上，用于电连接第一和第二金属柱; 以及形成在所述第二表面上用于电连接所述第二金属柱的第二电路层。 该半导体封装省去了用于在模塑料中形成导电柱的常规激光烧蚀和电镀工艺，从而节省制造时间和成本。

公开(公告)号：US20150162264A1

公开(公告)日：2015-06-11

申请号：US14273952

申请日：2014-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  G01K13/00 ,  G01L1/00 ,  H01L21/768 ,  H01L23/28

CPC classification number: H01L23/28 ,  B81B7/0061 ,  B81B7/007 ,  B81B2207/098 ,  G01L19/0076 ,  G01L19/147 ,  H01L23/10 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure.

Abstract translation: 提供了一种封装结构，其包括：具有带有凹槽的表面的晶片，封闭凹槽的开口端的薄膜和电触头; 芯片，其表面具有导电层，与凹部相对的表面和位于凹部周边的密封环，芯片设置在晶片上，密封环围绕薄膜，电触点位于 密封环外; 形成在晶片上用于封装芯片和电触点的密封剂; 多个次级导电线嵌入密封剂中，其一端从密封剂的顶表面露出，另一端与电触点电连接; 以及穿透晶片并与凹部连通的通孔，从而降低了封装结构的制造成本和尺寸。

公开(公告)号：US09041189B2

公开(公告)日：2015-05-26

申请号：US13659181

申请日：2012-10-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Chiang-Cheng Chang ,  Shih-Kuang Chiu

IPC: H01L23/538 ,  H01L21/00

CPC classification number: H01L21/00 ,  H01L21/568 ,  H01L23/3185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05558 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/82 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03

Abstract: A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements.

Abstract translation: 提供一种制造半导体封装的方法，包括：提供其上限定有多个芯片区域的载体，并且在每个芯片区域上形成连接单元; 在每个所述连接单元上设置半导体元件; 在载体和半导体元件上形成绝缘层; 以及在绝缘层上形成与半导体元件电连接的电路层。 由于在现有技术中仅在芯片区域而不是在整体载体上形成，所以连接单元在温度循环期间被防止膨胀或收缩，从而避免了半导体元件的位置偏差。