公开(公告)号：US20220344396A1

公开(公告)日：2022-10-27

申请号：US17861011

申请日：2022-07-08

Applicant: XINTEC INC.

Inventor： Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN

IPC: H01L27/146

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

公开(公告)号：US20170148694A1

公开(公告)日：2017-05-25

申请号：US15358098

申请日：2016-11-21

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU

IPC: H01L23/053 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L21/561 ,  G06K9/0004 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/16225

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

公开(公告)号：US20170040372A1

公开(公告)日：2017-02-09

申请号：US15226327

申请日：2016-08-02

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

Abstract translation: 本发明提供了一种制造芯片级感测芯片封装的方法，包括以下步骤：提供具有彼此相对的第一顶表面和第一底表面的感测装置晶片，由此感测装置晶片包括多个芯片 区域，并且每个芯片区域包括感测装置和与第一顶表面附近的感测芯片相邻的多个导电焊盘; 提供具有彼此相对的第二顶表面和第二底表面的盖晶片，并且通过在其间夹住第一粘合剂层将盖晶片的第二表面粘合到感测装置晶片的第一顶表面; 提供临时载体基板，并且通过在其间夹着第二粘合剂层将临时载体基板结合到盖晶片的第二顶表面; 形成连接到感测装置晶片的第一底表面上的每个导电焊盘的布线层; 在所述布线层上提供第一保护层; 去除所述临时载体基板和所述第二粘合剂层; 在所述第二顶表面上形成第二保护层; 去除第一保护层; 划片芯片区域以产生多个单独的芯片级感测芯片封装; 并移除第二保护层。

公开(公告)号：US20160049436A1

公开(公告)日：2016-02-18

申请号：US14819348

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687

Abstract: A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A colour filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the colour filter. The carrier substrate is removed.

Abstract translation: 制造芯片封装的方法包括提供至少具有光电二极管和互连层的半导体衬底。 互连层设置在半导体衬底的上表面上并且在光电二极管之上并且电连接到光电二极管。 至少在互连层上形成再分布电路。 再分配电路电连接到互连层。 在再分配电路上形成封装层。 随后，将载体衬底附接到包装层。 滤色器形成在半导体衬底的下表面上。 在滤色器下方形成微透镜模块。 移除载体衬底。

公开(公告)号：US20150228536A1

公开(公告)日：2015-08-13

申请号：US14618413

申请日：2015-02-10

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG ,  Shu-Ming CHANG ,  Tzu-Wen TSENG

IPC: H01L21/768 ,  H01L21/302 ,  H01L23/50

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/0657 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06165 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

Abstract translation: 提供了包括半导体衬底的芯片封装。 凹部位于半导体衬底中并与半导体衬底的侧边相邻，其中半导体衬底具有从凹部的底部突出的至少一个间隔件。 导电层设置在半导体衬底上并延伸到凹槽中。

公开(公告)号：US20150061102A1

公开(公告)日：2015-03-05

申请号：US14470159

申请日：2014-08-27

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14683 ,  H01L27/1469 ,  H01L31/02005 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/1204 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

Abstract translation: 提供了一种电子器件封装及其制造方法。 首先，提供半导体衬底，并且从凹部蚀刻其上表面。 第一隔离层形成在凹槽的上表面和侧壁上。 形成导电部件以实现凹部，并且在第一隔离层上形成导电焊盘以连接导电部件。 电子设备与晚餐表面上的半导体衬底组合，其中电子设备具有电连接到导电焊盘的连接焊盘。 半导体衬底从其下表面变薄以暴露导电部件。 第二隔离层形成在下表面下方并具有用于暴露导电部分的开口。 在第二隔离层下方和开口中形成再分布金属线，以电连接到导电部分。

公开(公告)号：US20150041995A1

公开(公告)日：2015-02-12

申请号：US14465015

申请日：2014-08-21

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31111 ,  H01L21/02271 ,  H01L21/561 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/02005 ,  H01L31/02327 ,  H01L31/1876 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11

Abstract: A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced.

Abstract translation: 芯片封装的制造方法包括以下步骤。 提供具有晶片和保护层的晶片结构。 晶片的第一开口与保护层的第二开口对准并与其连通。 具有第一厚度的第一绝缘层形成在从第二开口暴露的导电焊盘上，并且具有第二厚度的第二绝缘层形成在围绕第二开口的保护层的第一侧壁和晶片的第二侧壁上 围绕第一个开放。 蚀刻第一绝缘层和第二绝缘层，使得第一绝缘层被完全去除，并且第二绝缘层的第二厚度减小。

公开(公告)号：US20150035143A1

公开(公告)日：2015-02-05

申请号：US14516492

申请日：2014-10-16

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN

IPC: H01L31/02 ,  H01L31/18 ,  H01L33/58 ,  H01L33/62 ,  H01L27/146 ,  H01L31/0232

CPC classification number: H01L31/02005 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/02327 ,  H01L31/1876 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/0001 ,  H01L2924/1461 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 所述封装包括具有第一表面和与其相对的第二表面的半导体芯片，与所述第一表面相邻的至少一个导电焊盘以及从所述第二表面向所述第一表面延伸以露出所述导电焊盘的开口。 与第一表面相邻的口径大于与第二表面相邻的开口的口径。 绝缘层和再分配层（RDL）依次设置在第二表面上并延伸到开口的侧壁和底部，RDL通过开口与导电焊盘电连接。 钝化层覆盖RDL并且部分填充开口以在开口中的钝化层和导电垫之间形成空隙。 还公开了芯片封装的制造方法。

公开(公告)号：US20140225276A1

公开(公告)日：2014-08-14

申请号：US14171734

申请日：2014-02-03

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48151 ,  H01L2224/73207 ,  H01L2924/10156 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.

Abstract translation: 本公开的一个实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 电线层，其设置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中; 位于所述导线层和所述半导体基板之间的绝缘层; 设置在所述第一表面上的芯片; 以及设置在所述芯片和所述第一表面之间的导电结构。