公开(公告)号：US20060103017A1

公开(公告)日：2006-05-18

申请号：US11033994

申请日：2005-01-13

申请人： Takamasa Usui ,  Hideki Shibata ,  Tadashi Murofushi ,  Masakazu Jimbo ,  Hiroshi Hirayama

发明人： Takamasa Usui ,  Hideki Shibata ,  Tadashi Murofushi ,  Masakazu Jimbo ,  Hiroshi Hirayama

IPC分类号： H01L23/34

CPC分类号： H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device which comprises a wiring structure capable of reducing stress concentration at a boundary between a wiring and a low dielectric constant insulator even when the low dielectric constant insulator is used as an interlevel or interwiring insulator in a multilevel wiring, suppressing peeling-off of the insulator and having increased heat radiation efficiency is provided by comprising an insulator formed on a semiconductor substrate, a wiring formed in the insulator, and a network dummy formed in the insulator and disposed to be apart from the wiring.

摘要翻译： 即使在多层布线中使用低介电常数绝缘体作为层间或相互连接的绝缘体，也能够抑制布线与低介电常数绝缘体之间的边界处的应力集中的半导体装置，抑制剥离 通过包括形成在半导体衬底上的绝缘体，形成在绝缘体中的布线以及形成在绝缘体中并布置成与布线分开的网络虚拟来提供绝缘体并具有增加的散热效率。

公开(公告)号：US06946387B2

公开(公告)日：2005-09-20

申请号：US10650974

申请日：2003-08-29

申请人： Junichi Wada ,  Atsuko Sakata ,  Tomio Katata ,  Takamasa Usui ,  Masahiko Hasunuma ,  Hideki Shibata ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura

发明人： Junichi Wada ,  Atsuko Sakata ,  Tomio Katata ,  Takamasa Usui ,  Masahiko Hasunuma ,  Hideki Shibata ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76867 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76889

摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔 和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充 布线槽与Al接线。

公开(公告)号：US06919617B2

公开(公告)日：2005-07-19

申请号：US10462880

申请日：2003-06-17

申请人： Masaki Yamada ,  Hideki Shibata

发明人： Masaki Yamada ,  Hideki Shibata

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.

摘要翻译： 公开了一种半导体器件，其包括埋在第一布线槽中的第一金属布线，第一布线槽经由第一阻挡金属形成在形成于半导体基板上的第一绝缘层中，形成在第一金属布线上的第二绝缘层， 由形成在所述第二绝缘层中的通孔中的通过第二阻挡金属掩埋的金属形成，形成在所述第二绝缘层上的第三绝缘层，所述第二绝缘层中埋设有所述通孔插塞，以及第二金属布线， 通过具有不同于第二阻挡金属的层质量的层厚度的第三阻挡金属形成在第三绝缘层中的布线槽。

公开(公告)号：US20050121791A1

公开(公告)日：2005-06-09

申请号：US10778180

申请日：2004-02-17

申请人： Masaki Yamada ,  Hideki Shibata

发明人： Masaki Yamada ,  Hideki Shibata

IPC分类号： H01L21/768 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L27/04

CPC分类号： H01L23/53238 ,  H01L21/76838 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device includes a semiconductor substrate and a multi-layer wiring portion including insulating layers and wiring layers alternately stacked one on another on a main surface of the semiconductor substrate. The resistance value of a wiring layer located on an upper side of an adjacent pair of wiring layers is lower than or equal to that of a wiring layer located on a lower side of the adjacent pair, and the resistance value of the lowermost layer is higher than that of the uppermost layer. The specific inductive capacity of an insulating layer located on an upper side of an adjacent pair of insulating layers is higher than or equal to that of an insulating layer located on a lower side of the adjacent pair, and the specific inductive capacity of the lowermost layer is lower than that of the uppermost layer.

摘要翻译： 半导体器件包括半导体衬底和包括在半导体衬底的主表面上彼此交替堆叠的绝缘层和布线层的多层布线部分。 位于相邻的一对布线层的上侧的布线层的电阻值低于或等于位于相邻对的下侧的布线层的电阻值，并且最下层的电阻值较高 超过最上层。 位于相邻绝缘层的上侧的绝缘层的比感应电容高于或等于位于相邻对的下侧的绝缘层的电感电容，并且最下层的电感率 低于最上层。

公开(公告)号：US06541861B2

公开(公告)日：2003-04-01

申请号：US09893454

申请日：2001-06-29

申请人： Kazuyuki Higashi ,  Tamao Takase ,  Hideki Shibata

发明人： Kazuyuki Higashi ,  Tamao Takase ,  Hideki Shibata

IPC分类号： H01L2348

CPC分类号： H01L25/50 ,  H01L21/76251 ,  H01L21/84 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/1203 ,  H01L2221/6835 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, forming a semiconductor element in the semiconductor region, and removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.

公开(公告)号：US5917223A

公开(公告)日：1999-06-29

申请号：US760025

申请日：1996-12-04

申请人： Kazuya Ohuchi ,  Hideki Shibata

发明人： Kazuya Ohuchi ,  Hideki Shibata

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/66272 ,  H01L21/28052 ,  H01L21/823443 ,  H01L21/823835 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor device has a metal silicide on silicon conductor formed using a salicide process. The metal silicide layer of the conductor includes boron which improves the morphology and conductivity of the metal silicide layer. Implanting boron into the metal silicide layer or the metal to be silicided prevents the metal silicide from aggregating during a subsequent annealing or other heating process. This process allows narrower conductors to be formed without undesirable increases in the resistance of the metal silicide layer. The boron incorporating salicide process is compatible with CMOS processes.

摘要翻译： 半导体器件具有使用自对准硅化物工艺形成的硅导体上的金属硅化物。 导体的金属硅化物层包括改善金属硅化物层的形态和导电性的硼。 将硼注入金属硅化物层或要被硅化的金属防止金属硅化物在随后的退火或其它加热过程中聚集。 该方法允许形成较窄的导体，而不会不期望地增加金属硅化物层的电阻。 掺入硅化物工艺的硼与CMOS工艺兼容。

公开(公告)号：US5023679A

公开(公告)日：1991-06-11

申请号：US372462

申请日：1989-06-28

申请人： Hideki Shibata

发明人： Hideki Shibata

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/4925 ,  H01L29/4941

摘要： A semiconductor device comprises a MOSFET of LDD structure, in which the gate electrode structure comprises an oxide film interposed between a poly-Si layer and a refractory metal layer or a metal silicide. The oxide film prevents the metal or metal silicide from being diffused into the gate oxide film during the heating step included in the process of manufacturing the semiconductor device. Also, a side wall spacer is formed of poly-Si to achieve an electrical connection between the poly-Si layer and the layer of the metal having a high melting point or of the metal silicide so as to constitute a part of the gate electrode.

摘要翻译： 半导体器件包括LDD结构的MOSFET，其中栅电极结构包括介于多晶硅层和难熔金属层之间的氧化膜或金属硅化物。 在制造半导体器件的过程中包括的加热步骤期间，氧化膜防止金属或金属硅化物扩散到栅极氧化膜中。 此外，侧壁隔离物由多晶硅形成，以实现多晶硅层与具有高熔点的金属层或金属硅化物之间的电连接，从而构成栅电极的一部分。

公开(公告)号：US09184357B2

公开(公告)日：2015-11-10

申请号：US13310384

申请日：2011-12-02

申请人： Yoshiaki Sugizaki ,  Hideki Shibata ,  Masayuki Ishikawa ,  Hideo Tamura ,  Tetsuro Komatsu ,  Akihiro Kojima

发明人： Yoshiaki Sugizaki ,  Hideki Shibata ,  Masayuki Ishikawa ,  Hideo Tamura ,  Tetsuro Komatsu ,  Akihiro Kojima

IPC分类号： H01L33/00 ,  H01L33/44 ,  H01L33/38 ,  H01L33/62 ,  H01L23/00 ,  H01L25/075 ,  H01L33/34 ,  H01L33/48 ,  H01L33/58

CPC分类号： H01L33/62 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0753 ,  H01L33/0079 ,  H01L33/34 ,  H01L33/38 ,  H01L33/44 ,  H01L33/486 ,  H01L33/50 ,  H01L33/58 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/06132 ,  H01L2224/06152 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2933/0016 ,  H01L2933/0033 ,  H01L2933/0041 ,  H01L2933/0066 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.

摘要翻译： 一种制造发光器件的方法包括：形成包括发光层的多层体，使得其第一表面与透光性基板的第一表面侧相邻。 在与p层电极和n侧电极之间形成有第一和第二开口的与多层体的第一表面相对的第二表面侧上的电介质膜形成。 电介质膜上的种子金属和第一和第二开口的暴露表面形成将种子金属分离成p侧金属和n侧籽晶的p侧金属互连层和n侧金属互连层 金属，通过去除一部分种子金属。 在除去种子金属的空间中形成树脂。

公开(公告)号：US20120097972A1

公开(公告)日：2012-04-26

申请号：US13310384

申请日：2011-12-02

申请人： Yoshiaki SUGIZAKI ,  Hideki Shibata ,  Masayuki Ishikawa ,  Hideo Tamura ,  Tetsuro Komatsu ,  Akihiro Kojima

发明人： Yoshiaki SUGIZAKI ,  Hideki Shibata ,  Masayuki Ishikawa ,  Hideo Tamura ,  Tetsuro Komatsu ,  Akihiro Kojima

IPC分类号： H01L33/50 ,  H01L33/30

CPC分类号： H01L33/62 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0753 ,  H01L33/0079 ,  H01L33/34 ,  H01L33/38 ,  H01L33/44 ,  H01L33/486 ,  H01L33/50 ,  H01L33/58 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/06132 ,  H01L2224/06152 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2933/0016 ,  H01L2933/0033 ,  H01L2933/0041 ,  H01L2933/0066 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.

摘要翻译： 一种制造发光器件的方法包括：形成包括发光层的多层体，使得其第一表面与透光性基板的第一表面侧相邻。 在与p层电极和n侧电极之间形成有第一和第二开口的与多层体的第一表面相对的第二表面侧上的电介质膜形成。 电介质膜上的种子金属和第一和第二开口的暴露表面形成将种子金属分离成p侧金属和n侧籽晶的p侧金属互连层和n侧金属互连层 金属，通过去除一部分种子金属。 在除去种子金属的空间中形成树脂。

公开(公告)号：USRE43320E1

公开(公告)日：2012-04-24

申请号：US12202037

申请日：2008-08-29

申请人： Masaki Yamada ,  Hideki Shibata

发明人： Masaki Yamada ,  Hideki Shibata

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.

摘要翻译： 公开了一种半导体器件，其包括埋在第一布线槽中的第一金属布线，第一布线槽经由第一阻挡金属形成在形成于半导体基板上的第一绝缘层中，形成在第一金属布线上的第二绝缘层， 由形成在所述第二绝缘层中的通孔中的通过第二阻挡金属掩埋的金属形成，形成在所述第二绝缘层上的第三绝缘层，所述第二绝缘层中埋设有所述通孔插塞，以及第二金属布线， 通过具有不同于第二阻挡金属的层质量的层厚度的第三阻挡金属形成在第三绝缘层中的布线槽。