公开(公告)号：US20240274522A1

公开(公告)日：2024-08-15

申请号：US18645381

申请日：2024-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hungen Hsu ,  Wei-Tien Shen ,  Kuo-Ching Hsu

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/16

CPC分类号： H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/165 ,  H01L28/60

摘要： Embodiments provide a package substrate. The package substrate includes a substrate and a semiconductor device. The substrate includes a cavity hole therein. The semiconductor device is embedded in the cavity hole. The semiconductor device includes a first device component and a second device component. The first device component has a first pad, a second pad, and a first trench capacitor. The second device component has a third pad, a fourth pad, and a second trench capacitor. A backside of the first device component is bonded to a backside of the second device component, and the first pad has an area less than an area of the third pad, and the second pad has an area less than an area of the fourth pad.

公开(公告)号：US12062603B2

公开(公告)日：2024-08-13

申请号：US18079555

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo

IPC分类号： H01L23/498 ,  H01L21/285 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482

CPC分类号： H01L23/49827 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L21/28568 ,  H01L23/49866 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/95001 ,  H01L2924/35121

摘要： Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.

公开(公告)号：US20240266270A1

公开(公告)日：2024-08-08

申请号：US18166192

申请日：2023-02-08

申请人： General Electric Company

发明人： Arun Virupaksha Gowda ,  Ljubisa D. Stevanovic ,  Christopher James Kapusta ,  Robert Dwayne Gossman ,  Risto Ilkka Sakari Tuominen

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/486 ,  H01L23/49861

摘要： A semiconductor assembly includes a semiconductor device and a POL-RDL package coupled to said device. The device includes an upper surface, a gate pad and at least one source pad disposed on said upper surface. The POL-RDL package includes a dielectric layer having at least one source pad electrically coupled to said at least one source pad of said device and at least one contact pad disposed. At least one trace connection having a resistivity value electrically couples said at least one source pad of said POL-RDL package to said at least one contact pad.

公开(公告)号：US20240266267A1

公开(公告)日：2024-08-08

申请号：US18637737

申请日：2024-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： PEI CHENG FAN

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/73204

摘要： The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.

公开(公告)号：US12057324B2

公开(公告)日：2024-08-06

申请号：US18090918

申请日：2022-12-29

申请人： Shanghai Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC OPTO Electronics Co., Ltd.

发明人： Xuhui Peng ,  Kerui Xi ,  Tingting Cui ,  Feng Qin ,  Jie Zhang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L21/4853 ,  H01L21/486 ,  H01L21/4896 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2924/37001

摘要： A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.

公开(公告)号：US12046548B2

公开(公告)日：2024-07-23

申请号：US18307091

申请日：2023-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/053 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83

摘要： A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure having a conductive pad. The substrate structure includes a first insulating layer under the redistribution structure. The substrate structure includes a conductive via structure passing through the first insulating layer. The conductive via structure is under and electrically connected with the conductive pad. The substrate structure includes a second insulating layer disposed between the redistribution structure and the first insulating layer. The chip package includes a first chip over the redistribution structure and electrically connected to the conductive via structure through the redistribution structure. The chip package includes a second chip under the substrate structure.

公开(公告)号：US12040279B2

公开(公告)日：2024-07-16

申请号：US17738460

申请日：2022-05-06

申请人： Micron Technology, Inc.

发明人： Matthew Monroe

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/5384 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16225

摘要： A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.

公开(公告)号：US12033883B2

公开(公告)日：2024-07-09

申请号：US17805557

申请日：2022-06-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hsiang Hu ,  Chung-Shi Liu ,  Hung-Jui Kuo ,  Ming-Da Cheng

IPC分类号： H01L21/683 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L21/6835 ,  H01L21/2885 ,  H01L21/486 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/19 ,  H01L2224/83005

摘要： A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.

公开(公告)号：US20240224543A1

公开(公告)日：2024-07-04

申请号：US18091264

申请日：2022-12-29

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton

IPC分类号： H10B80/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC分类号： H10B80/00 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827

摘要： Multi-chip/die device including a logic IC die facing a first side of a glass substrate and a memory IC die facing, and coupled to, the logic IC die. First ones of first metallization features of the logic IC die are coupled to through-glass vias extending through a thickness of the glass substrate. The memory IC die is coupled to second ones of the first metallization features, either directly or by way of other through-glass vias. The logic IC die and/or memory IC die may be directly bonded to the through-glass vias or may be attached by solder. The logic IC die or memory IC die may be embedded within the glass substrate. Through-glass vias within a region beyond an edge of the memory IC die may couple the logic IC die to a host component either through a routing structure built up adjacent the memory IC die, or through solder features attached to the glass substrate adjacent to the memory IC die.

公开(公告)号：US20240223283A1

公开(公告)日：2024-07-04

申请号：US18429960

申请日：2024-02-01

申请人： L. Pierre de Rochemont

发明人： L. Pierre de Rochemont

IPC分类号： H04B10/69 ,  H01L21/48 ,  H01L23/528 ,  H01L23/538 ,  H01L23/66 ,  H01L25/11 ,  H03H3/00 ,  H03H7/06 ,  H03H7/52 ,  H03H11/42 ,  H04L7/00 ,  H04Q11/00

CPC分类号： H04B10/6972 ,  H01L21/486 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L25/117 ,  H03H3/00 ,  H03H7/06 ,  H03H7/52 ,  H03H11/42 ,  H04L7/0087 ,  H04Q11/0071 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6661

摘要： A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.