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公开(公告)号：US20180006797A1
公开(公告)日：2018-01-04
申请号：US15703792
申请日：2017-09-13
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tapas NANDY , Nitin GUPTA
CPC classification number: H04L7/0008 , G06F1/10 , H04J3/0685 , H04L1/0026 , H04L5/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L7/0337
Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.
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公开(公告)号：US09832008B2
公开(公告)日：2017-11-28
申请号：US14986152
申请日：2015-12-31
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Chowdhary , Vivek Uppal , Alok Kaushik , Sajal Kumar Mandal , Tapas Nandy , Sanjeev Chopra
CPC classification number: H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
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公开(公告)号：US09813024B2
公开(公告)日：2017-11-07
申请号：US14985759
申请日：2015-12-31
Applicant: STMicroelectronics International N.V.
Inventor： Vinod Kumar
IPC: H03F1/02 , H01L29/78 , H01L29/94 , H01L29/66 , H01L21/84 , G05F3/16 , H03K17/687 , H03L7/093 , H03F3/193 , H01L29/786
CPC classification number: H03F1/0205 , G05F3/16 , H01L21/84 , H01L29/66181 , H01L29/7831 , H01L29/78603 , H01L29/78648 , H01L29/94 , H03F3/193 , H03F2200/451 , H03K17/687 , H03L7/093
Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.
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公开(公告)号：US09800204B2
公开(公告)日：2017-10-24
申请号：US14219786
申请日：2014-03-19
Applicant: STMicroelectronics International N.V.
Inventor： Vinod Kumar
IPC: H03F1/02 , H01L29/78 , H01L29/94 , H01L29/66 , H01L21/84 , G05F3/16 , H03K17/687 , H03L7/093 , H03F3/193 , H01L29/786
CPC classification number: H03F1/0205 , G05F3/16 , H01L21/84 , H01L29/66181 , H01L29/7831 , H01L29/78603 , H01L29/78648 , H01L29/94 , H03F3/193 , H03F2200/451 , H03K17/687 , H03L7/093
Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.
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公开(公告)号：US20170301072A1
公开(公告)日：2017-10-19
申请号：US15636294
申请日：2017-06-28
Inventor： Mahesh CHANDRA , Antoine DROUOT
CPC classification number: G06T5/20 , G06K9/4604 , G06K9/4671 , G06K9/56 , G06T5/002 , G06T11/60 , G06T2207/10016
Abstract: Various embodiments provide an optimized image filter. The optimized image and video obtains an input image and selects a target pixel for modification. Difference values are then determined between the selected target pixel and each reference pixel of a search area. Subsequently, a weighting function is used to determine weight values for each of the reference pixels of the search area based on their respective difference value. The selected target pixel is then modified by the optimized image filter using the determined weight values. A new target pixel in an apply patch is then selected for modification. The new target pixel is modified using the previously determined weight values reassigned to a new set of reference pixels. The previously determined weight values are reassigned to the new set of reference pixels based on each of the new set of reference pixels' position relative to the new target pixel.
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Patent Agency Ranking
公开(公告)号：US20170297332A1
公开(公告)日：2017-10-19
申请号：US15636491
申请日：2017-06-28
Applicant: STMicroelectronics, Inc. , STMICROELECTRONICS S.R.L. , STMicroelectronics International N.V.
Inventor： Simon DODD , Joe SCHEFFELIN , Dave HUNT , Matt GIERE , Dana GRUENBACHER , Faiz SHERMAN
CPC classification number: B05B17/0607 , B05B17/0638 , B05B17/0684 , B41J2/14016 , B41J2/14024 , B41J2/14056 , B41J2/14072 , B41J2/1433 , B41J2/1601 , B41J2/1632 , B41J2/175 , B41J2/17526 , B41J2/1753 , B41J2002/14338 , B41J2002/14491 , H05K1/0212 , H05K1/111 , H05K1/181 , Y10T29/49119
Abstract: The present disclosure is directed to a microfluidic die that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second contacts are coupled to each other and coupled to ground. The die includes a plurality of contact pads, a first signal line coupled to the plurality of second contacts and to a first one of the plurality of contact pads, and a plurality of second signal lines, each second signal line being coupled to one of the plurality of first contacts, groups of the second signal lines being coupled together to drive a group of the plurality of heaters with a single signal, each group of the second signal lines being coupled to a remaining one of the plurality of contact pads.
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公开(公告)号：US20170294898A1
公开(公告)日：2017-10-12
申请号：US15632202
申请日：2017-06-23
Applicant: STMicroelectronics International N.V.
Inventor： Neha Bhargava , Ankur Bal
CPC classification number: H03H17/0283 , H03H17/0275 , H03H17/0664 , H03H17/0671 , H03H21/0027 , H03H2017/0245
Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
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公开(公告)号：US20170288693A1
公开(公告)日：2017-10-05
申请号：US15465305
申请日：2017-03-21
Applicant: STMicroelectronics International N.V.
Inventor： Ashish Sharma Kumar , Rajeev Jain , Chandrajit Debnath
Abstract: A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided.
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公开(公告)号：US09775251B2
公开(公告)日：2017-09-26
申请号：US14957752
申请日：2015-12-03
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Patrik Arno , Eric Cirot
CPC classification number: H05K3/32 , H02M1/08 , H02M3/1588 , H02M7/483 , H02M2001/0054 , H02M2007/4835 , H03K17/162 , Y02B70/1466 , Y02B70/1491
Abstract: A circuit is for controlling a power transistor of a DC/DC converter. The circuit may include first and second first transistors coupled in series between a first reference voltage and a control terminal of the power transistor, the first and second transistors defining a first junction node. The circuit may include third and fourth transistors coupled in series between the control terminal and a second reference voltage, the third and fourth transistors defining a second junction node. The first and second transistors may have a first conductivity type different from a second conductivity type of the third and fourth transistors. The circuit may include a capacitive element coupled between the first and second junction nodes.
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公开(公告)号：US09762383B2
公开(公告)日：2017-09-12
申请号：US15160368
申请日：2016-05-20
Inventor： Julien Saade , Abdelaziz Goulahsen
CPC classification number: H04L9/001 , H04L25/03 , H04L25/03866 , H04L2209/34
Abstract: A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal. The scrambled signal is monitored to detect occurrences of one or more data patterns. In response to the detection of one or more occurrences, one or more actions are taken to protect data in the output signal.
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