公开(公告)号：US20150137330A1

公开(公告)日：2015-05-21

申请号：US14572288

申请日：2014-12-16

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Rachid TAIBI ,  Cédrick CHAPPAZ ,  Lea DI CIOCCIO ,  Laurent-Luc CHAPELON

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L22/12 ,  H01L22/14 ,  H01L27/0688 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

Abstract translation: 三维集成结构可以包括分别包括两条金属线的两个组装的集成电路，以及穿过集成电路中的一个的至少两个空腔，并分别与两个金属线电接触地分开开放到两个位置。 空腔的尺寸可以将测量装置放置在空腔的底部，并与两个位置电接触。

公开(公告)号：US20150118824A1

公开(公告)日：2015-04-30

申请号：US14526005

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Emmanuel Josse ,  Olivier Nier

IPC: H01L21/762 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/324 ,  H01L21/76237 ,  H01L21/84 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7847

Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.

Abstract translation: 本发明的一个或多个实施方案涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层和绝缘体层的半导体结构的表面中形成至少两个第一方向的第一沟槽， 要在半导体结构中形成的至少一个第一晶体管的第一尺寸; 执行第一退火以降低绝缘层的粘度; 以及在所述第一退火之后的表面中，在限定所述至少一个晶体管的第二维度的第二方向上形成至少两个第二沟槽。

公开(公告)号：US20150118823A1

公开(公告)日：2015-04-30

申请号：US14526053

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。

公开(公告)号：US20150109057A1

公开(公告)日：2015-04-23

申请号：US14515342

申请日：2014-10-15

Applicant: STMicroelectronics SA

Inventor： Emmanuel Rouat

IPC: H03G3/30 ,  H03F3/45

CPC classification number: H03G3/30 ,  H03F3/45071 ,  H03F2203/45178 ,  H03F2203/45202 ,  H03F2203/45336 ,  H03F2203/45528 ,  H03G1/0088 ,  H03G3/001

Abstract: A resistive ladder has first, second and third resistors coupled in series between first and second voltage terminals. A first node of the first resistor is coupled to the first voltage terminal and a first node of the third resistor is coupled to the second voltage terminal. A voltage selection unit has a first input coupled to a first node of the second resistor and a second input coupled to a second node of the second resistor and is adapted to selectively couple one of the first and second inputs to an output node of said resistive ladder. The resistive ladder also includes a first switch coupled between a second node of the third resistor and the second voltage terminal.

Abstract translation: 电阻梯具有在第一和第二电压端子之间串联耦合的第一，第二和第三电阻器。 第一电阻器的第一节点耦合到第一电压端子，并且第三电阻器的第一节点耦合到第二电压端子。 电压选择单元具有耦合到第二电阻器的第一节点的第一输入和耦合到第二电阻器的第二节点的第二输入，并且适于选择性地将第一和第二输入中的一个耦合到所述电阻的输出节点 阶梯。 电阻梯还包括耦合在第三电阻器的第二节点和第二电压端子之间的第一开关。

公开(公告)号：US09000964B2

公开(公告)日：2015-04-07

申请号：US14294300

申请日：2014-06-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

IPC: H03M1/00 ,  H03M1/08 ,  H03K3/013 ,  G11C27/02 ,  H03K19/0185

CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CNGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CNGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

公开(公告)号：US20150091089A1

公开(公告)日：2015-04-02

申请号：US14499545

申请日：2014-09-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Olivier Rozeau

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/515 ,  H01L29/0843 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/78

Abstract: A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers.

Abstract translation: MOS晶体管具有由沉积在衬底上的高介电常数材料制成的栅极绝缘体层。 栅极绝缘体层以恒定的厚度延伸到栅极堆叠之下和之外。 通过栅极绝缘体层的延伸超过栅极叠层的侧面，在栅极叠层的任一侧上形成具有低介电常数的隔板并与衬底垂直分离。 低介电常数的间隔物优选为空气间隔物。

公开(公告)号：US08980702B2

公开(公告)日：2015-03-17

申请号：US14177614

申请日：2014-02-11

Applicant: Commissariat a l'Energie Atomique et aux ene Alt ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Maud Vinet

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.

Abstract translation: 一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层， 所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。

公开(公告)号：US20150061023A1

公开(公告)日：2015-03-05

申请号：US14450597

申请日：2014-08-04

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L29/66 ,  H01L27/12 ,  H01L29/747 ,  H01L29/78

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

Abstract translation: 本发明涉及具有静电放电保护装置的IC。 在绝缘层上存在厚度为50nm以下的绝缘绝缘层和第一和第二双极晶体管，一个为npn晶体管，另一个为pnp晶体管。 第一晶体管的基极与第二晶体管的集电极合并，第二晶体管的基极与第一晶体管的集电极合并。 第一和第二双极晶体管被配置为选择性地在保护装置的两个电极之间传导放电电流。 在绝缘层下方存在第一半导体接地层，被电偏压，延伸直到其与第一双极晶体管的基极相连，表现出与第一双极晶体管的基极相同的第一类掺杂，掺杂 密度至少十倍以上。

公开(公告)号：US20150028488A1

公开(公告)日：2015-01-29

申请号：US14339630

申请日：2014-07-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Jean-Philippe COLONNA ,  Perceval COUDRAIN

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L21/30604 ,  H01L21/4853 ,  H01L21/6836 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13186 ,  H01L2224/1356 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract translation: 本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤 ，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫 在所述导电元件上。

公开(公告)号：US08913457B2

公开(公告)日：2014-12-16

申请号：US14271165

申请日：2014-05-06

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics, SA

Inventor： Nishu Kohli ,  Robin M. Wilson

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract translation: 存储器电路包括响应于内部时钟的第一边缘可操作的存储器组件。 存储电路还包括响应系统时钟产生内部时钟的内部时钟产生电路。 响应于系统时钟的上升沿和下降沿都产生内部时钟的第一个边沿。