公开(公告)号：US20180144963A1

公开(公告)日：2018-05-24

申请号：US15360187

申请日：2016-11-23

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Mohsen H. Mardi ,  Tien-Yu Lee ,  Ivor G. Barber ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L21/673 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/67333 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/67109 ,  H01L23/3185 ,  H01L23/3675 ,  H01L24/16 ,  H01L2224/16227

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

公开(公告)号：US09967057B1

公开(公告)日：2018-05-08

申请号：US15345353

申请日：2016-11-07

Applicant: Xilinx, Inc.

Inventor： Nihat E. Tunali ,  Michael Wu ,  Hai-Jo Tarn ,  Christopher H. Dick

IPC: H04L27/06 ,  H04L1/00 ,  G06F17/18

CPC classification number: H04L1/0045 ,  G06F17/10 ,  H04L25/067

Abstract: A method includes communicating data in a channel. Received symbols for the data correspond to points of a received symbol space respectively. First and second dimensions of the received symbol space correspond to a real part and an imaginary part of the received symbols respectively. A first received symbol for the data is obtained. A first region of the received symbol space for the first received symbol is determined. A first regression model associated with the first region and a first bit of the first received symbol is retrieved from a storage. The first regression model includes a plurality of regressors. A first log-likelihood ratio (LLR) for the first bit of the first received symbol is estimated using the first regression model.

公开(公告)号：US09960227B2

公开(公告)日：2018-05-01

申请号：US14024543

申请日：2013-09-11

Applicant: Xilinx, Inc.

Inventor： Michael J. Hart ,  James Karp

IPC: H01L23/48 ,  H01L23/544 ,  H01L23/58 ,  H01L23/52 ,  H01L29/02 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L25/075 ,  H01L21/48 ,  H01L25/04 ,  H01L21/66 ,  H01L23/60 ,  H01L23/498

CPC classification number: H01L29/02 ,  H01L21/4846 ,  H01L21/78 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/585 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/042 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/115 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/752 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2224/81

Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.

公开(公告)号：US20180113787A1

公开(公告)日：2018-04-26

申请号：US15334182

申请日：2016-10-25

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Kumar Deepak

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3632 ,  G06F11/3648

Abstract: Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.

公开(公告)号：US09954534B2

公开(公告)日：2018-04-24

申请号：US15267880

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin ,  Henri Fraisse

IPC: H03K19/177 ,  H01L25/00 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K19/1776 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0372 ,  H03K3/0375 ,  H03K19/17728

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.

公开(公告)号：US09935870B2

公开(公告)日：2018-04-03

申请号：US14995839

申请日：2016-01-14

Applicant: Xilinx, Inc.

Inventor： Henri Fraisse

IPC: H04L12/701 ,  H04L12/707 ,  H04L12/761 ,  H04L12/933

CPC classification number: H04L45/24 ,  H04L45/16 ,  H04L49/101 ,  H04L49/15 ,  H04L49/253

Abstract: Methods and systems are disclosed for selecting channels for routing signals in a multi-channel switching network. In an example implementation, pairs of the signals that can be routed together over one channel in the multi-channel switching network are determined. A model graph is generated that has a respective vertex for each of the signals. The model graph also includes respective edges for the determined pairs connecting vertices corresponding to signals of the pair. A subset of the edges that includes a maximum number of disjoint edges is determined. Pairs of signals represented by the respective vertices connected by the edge are routed over a respective one of the channels. For vertices not connected to an edge in the subset, the signals represented by the vertices are routed via a respective one of the channels.

公开(公告)号：US20180083633A1

公开(公告)日：2018-03-22

申请号：US15267880

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin ,  Henri Fraisse

IPC: H03K19/177 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K19/1776 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0372 ,  H03K3/0375 ,  H03K19/17728

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.

公开(公告)号：US20180083096A1

公开(公告)日：2018-03-22

申请号：US15272292

申请日：2016-09-21

Applicant: Xilinx, Inc.

Inventor： Jing Jing ,  Shuxian Wu ,  Jane Sowards

IPC: H01L29/06 ,  H01L21/761

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L21/823481

Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

公开(公告)号：US20180074533A1

公开(公告)日：2018-03-15

申请号：US15266947

申请日：2016-09-15

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  John K. Jennings

IPC: G05F1/46

CPC classification number: G05F1/468

Abstract: An integrated circuit includes a reference voltage circuit. The reference voltage circuit includes a bipolar junction transistor (BJT) configured to receive a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage, and receive a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage. The reference voltage circuit includes a switched capacitor circuit configured to provide a reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage.

公开(公告)号：US09916129B1

公开(公告)日：2018-03-13

申请号：US14527677

申请日：2014-10-29

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Nishit Patel ,  James J. Murray

IPC: G06F5/14 ,  G06F13/28

CPC classification number: G06F5/14 ,  G06F13/28 ,  G06F2205/126

Abstract: Circuits and methods are disclosed that allow devices to control the flow of DMA transfers to or from the devices using a token based protocol. In one example implementation, a DMA circuit includes a transfer control circuit that performs data transfers over a first data channel of a device, when transactions on the first data channel are enabled. The DMA circuit includes a flow control circuit that increments a token count for a data channel of a device when a token for the data channel is received and decrements the token count for each data transfer on the data channel performed by the DMA circuit. The flow control circuit enables data transfers on the data channel when the token count is greater than 0, and otherwise, disables data transfers on the data channel.