公开(公告)号：US20180218947A1

公开(公告)日：2018-08-02

申请号：US15423326

申请日：2017-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Peng Xu ,  Chun Wing Yeung

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/321 ,  H01L29/08 ,  H01L29/417 ,  H01L21/66

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L22/20 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545

Abstract: A method and system are disclosed herein for an adjustable effective fin height in a gate region of a finFET device. Fin structures, each having a first height, a fin, an oxide liner, and a nitride liner, are formed. A first portion of the nitride liner is removed. A first portion of the oxide liner is removed. A second portion of the nitride liner in a gate portion of the finFET. Source/drain(s) are formed, and a nitride spacer between the source/drain and the gate portion is formed. A second portion of the oxide liner is exposed by removing the second portion of the nitride liner, exposing a second portion of the fin, wherein the first and second exposed portions of the fin being an effective fin height in the gate portion.

公开(公告)号：US10037919B1

公开(公告)日：2018-07-31

申请号：US15609603

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823487 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A structure and method of making a semiconductor device includes a single-gated vertical field effect transistor (VFET), that has a first fin on a first bottom source/drain region, a gate of a first work force metal (WFM) surrounding the first fin, and a single gate contact connected to the first WFM. Also included is a double-gated VFET, that has a second fin on a second bottom source/drain region, a first gate of the first WFM disposed on a first side of the second fin, a second wider gate of a second WFM disposed on a second side of the second fin, a first gate contact contacting the first narrow gate, and a second gate contact contacting the second wider gate of the second WFM on the second side.

公开(公告)号：US10026824B1

公开(公告)日：2018-07-17

申请号：US15408540

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Andre Labonte ,  Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Guillaume Bouche

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L29/40 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/8234

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US10014370B1

公开(公告)日：2018-07-03

申请号：US15491420

申请日：2017-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel semiconductor (VOCS) structure and forming a gate structure around the VOCS structure and above the initial bottom spacer. In this example, the method also includes performing at least one etching process to remove at least a portion of the initial bottom spacer that is positioned vertically under the gate structure so as to thereby result in the formation of an air gap that is positioned under the gate structure, wherein the air gap extends around at least a majority of a perimeter of the VOCS structure, and forming a replacement bottom spacer above the semiconductor substrate and adjacent the air gap.

公开(公告)号：US10002965B2

公开(公告)日：2018-06-19

申请号：US15298648

申请日：2016-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L21/225 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US10002792B2

公开(公告)日：2018-06-19

申请号：US15624156

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US09991352B1

公开(公告)日：2018-06-05

申请号：US15651282

申请日：2017-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ali Razavieh ,  Ruilong Xie ,  Steven Bentley

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/42364 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.

公开(公告)号：US09972494B1

公开(公告)日：2018-05-15

申请号：US15351747

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Ruilong Xie

IPC: H01L21/3213 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L21/28123 ,  H01L21/26513 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.

公开(公告)号：US20180122919A1

公开(公告)日：2018-05-03

申请号：US15337254

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/28026 ,  H01L21/3213 ,  H01L29/401 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/66795

Abstract: One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.

公开(公告)号：US20180122913A1

公开(公告)日：2018-05-03

申请号：US15338925

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/417 ,  H01L23/525 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L23/5256 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.