公开(公告)号：US20180006111A1

公开(公告)日：2018-01-04

申请号：US15197944

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.

公开(公告)号：US09853110B2

公开(公告)日：2017-12-26

申请号：US14927765

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Sean X. Lin

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/288 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/288 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.

公开(公告)号：US09847390B1

公开(公告)日：2017-12-19

申请号：US15434205

申请日：2017-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L29/161 ,  H01L29/786 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78684

Abstract: This disclosure relates to forming a wrap-around contact on a nanosheet transistor, the method including: forming an etch-stop layer over a continuous outer surface of a raised source/drain (S/D) region of the nanosheet transistor; forming a sacrificial layer over the etch-stop layer, the etch-stop layer including a different material than the sacrificial layer; depositing a dielectric layer over the sacrificial layer; removing an upper portion of the dielectric layer to expose a portion of the sacrificial layer; removing the sacrificial layer selective to the etch-stop layer; and depositing a conductor in the removed upper portion of the dielectric layer to form a wrap-around contact and a second contact.

公开(公告)号：US09837404B2

公开(公告)日：2017-12-05

申请号：US15082242

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US09818836B1

公开(公告)日：2017-11-14

申请号：US15486387

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Dong-Ick Lee

IPC: H01L29/51 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a FinFET structure involves forming a gate cut within a sacrificial gate layer and backfilling the gate cut opening with etch selective dielectric materials. Partial etching of one of the dielectric materials can be used to increase the distance between the gate cut (isolation) structure and an adjacent fin relative to methods that do not perform a backfilling step using etch selective materials.

公开(公告)号：US09818823B2

公开(公告)日：2017-11-14

申请号：US15202994

申请日：2016-07-06

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US09806078B1

公开(公告)日：2017-10-31

申请号：US15341240

申请日：2016-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher Prindle ,  Tenko Yamashita ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Soon-Cheon Seo

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first and second plurality of gates, depositing a first liner on the structure, depositing a fill material at a level along inner portions of the first liner between the gates adjacent to the one or more fin, removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner defining a first thickness, and depositing a second liner having a second thickness over the gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.

公开(公告)号：US20170309714A1

公开(公告)日：2017-10-26

申请号：US15639095

申请日：2017-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L29/45 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a source/drain region of a transistor device, performing a recess etching process on the initial conductive source/drain structure to thereby define a stepped conductive source/drain structure with a cavity defined therein, forming a non-conductive structure in the cavity, forming a layer of insulating material above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, forming a gate contact opening in the layer of insulating material and forming a conductive gate contact in the gate contact opening that is conductively coupled to the gate structure.

公开(公告)号：US09799748B1

公开(公告)日：2017-10-24

申请号：US15398335

申请日：2017-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/3085 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming a stack of semiconductor material layers above a substrate. The stack includes at least one first semiconductor material layer and at least one second semiconductor material layer. A first etching process is performed on the stack to define cavities. The cavities expose end portions of the first and second semiconductor material layers. Portions of the first semiconductor material layer are removed to define end recesses. A layer of insulating material is formed in the end recesses and at least partially fills the cavities. A second etching process is performed on the stack to remove end portions of the at least one second semiconductor material layer and to remove portions of the layer of insulating material in the cavities not disposed between the first and second semiconductor material layers so as to form inner spacers on ends of the at least one first semiconductor material layer.

公开(公告)号：US09793157B2

公开(公告)日：2017-10-17

申请号：US15342440

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.