公开(公告)号：US09940299B2

公开(公告)日：2018-04-10

申请号：US15393234

申请日：2016-12-28

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Hae-Chang Lee ,  Brian S. Leibowitz ,  Simon Li ,  Nhat M. Nguyen

IPC: G06F3/00 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H04L1/20 ,  H04L1/00 ,  H04L25/02

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02D50/10

Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

公开(公告)号：US09934851B2

公开(公告)日：2018-04-03

申请号：US15040921

申请日：2016-02-10

Applicant: Rambus Inc.

Inventor： Mark D. Kellam ,  Gary Bela Bronner

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/00 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2418 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143

Abstract: A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.

公开(公告)号：US20180091705A1

公开(公告)日：2018-03-29

申请号：US15714483

申请日：2017-09-25

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  Thomas Vogelsang

IPC: H04N5/217

CPC classification number: H04N5/2173 ,  G02B5/1842 ,  G02B27/0056 ,  G02B27/0068 ,  G02B27/4205

Abstract: An imaging system with a diffractive optic captures an interference pattern responsive to light from an imaged scene to represent the scene in a spatial-frequency domain. The sampled frequency-domain image data has properties that are determined by the point-spread function of diffractive optic and characteristics of scene. An integrated processor can modified the sampled frequency-domain image data responsive to such properties before transforming the modified frequently-domain image data into the pixel domain.

公开(公告)号：US09929883B2

公开(公告)日：2018-03-27

申请号：US14860544

申请日：2015-09-21

Applicant: Rambus Inc.

Inventor： E-Hung Chen

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04L25/03146

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

公开(公告)号：US09923602B2

公开(公告)日：2018-03-20

申请号：US15138077

申请日：2016-04-25

Applicant: Rambus Inc.

Inventor： John W. Poulton ,  Frederick A. Ware ,  Carl W. Werner

IPC: H02H3/22 ,  H04B3/56 ,  H04L25/02 ,  G06F13/40 ,  H04B3/54 ,  H04B10/50 ,  H04B10/40 ,  H04B10/073 ,  H04B1/04

CPC classification number: H04B3/56 ,  G06F13/4072 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/15311 ,  H03F3/24 ,  H04B3/54 ,  H04B10/0731 ,  H04B10/40 ,  H04B10/50 ,  H04B2001/0408 ,  H04L25/0272 ,  H01L2924/00014

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

公开(公告)号：US09916196B2

公开(公告)日：2018-03-13

申请号：US14631570

申请日：2015-02-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US20180069556A1

公开(公告)日：2018-03-08

申请号：US15644632

申请日：2017-07-07

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

IPC: H03L7/16 ,  H03L7/24 ,  H03L7/099 ,  H03K5/00 ,  H03L7/06 ,  H03K3/03 ,  H03K5/14 ,  H03K5/13

CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

公开(公告)号：US09905286B2

公开(公告)日：2018-02-27

申请号：US15646024

申请日：2017-07-10

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4072

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G06F13/405 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

公开(公告)号：US20180053544A1

公开(公告)日：2018-02-22

申请号：US15552569

申请日：2016-02-22

Applicant: RAMBUS INC.

Inventor： Frederick A. WARE ,  Ely K. TSERN ,  John Eric LINDSTADT ,  Thomas J. GIOVANNINI ,  Scott C. BEST ,  Kenneth L. WRIGHT

IPC: G11C11/4093 ,  H01L25/18 ,  G11C11/4096 ,  G11C11/4076 ,  H01L25/065 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/824 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/45099

Abstract: A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US09886993B2

公开(公告)日：2018-02-06

申请号：US15332785

申请日：2016-10-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.