Abstract:
Inhibitors of E-, P- and L-selectin binding are synthesized by an aldol addition reaction between a glycoside aldehyde precursor and dihydroxyacetone phosphate or a derivative thereof. The addition reaction is catalyzed by aldolase. The inhibitors exhibit an activity comparable to sialyl Lewis X with respect to the E-selectin binding assay and high activities in the P- and L-selectin binding assays. The inhibitors are employable for blocking neutrophil inflamatory conditions.
Abstract:
Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.
Abstract:
A fully automatic simulation system for an input device permits storage in advance of executable applications and associated simulation setting flies into a database, and then combination of the detection, automatic data searching and matching, transmission and conversion, enabling rapid and convenient operation by the users, whenever they operate various applications or whether they adopt a keyboard, mouse or joystick as the simulation controller.
Abstract:
Cathepsin S inhibitors having formula (I), (II), (III) or (IV) as shown in the specification. These inhibitors can be used to treat cancer and autoimmune/inflammatory diseases.
Abstract:
Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
Abstract:
A foldable electric device comprises a first member, a second member and a pivot portion. The pivot portion is used to pivot the first member and the second member. The first member comprises a first cushion pad and a first magnetic component. The first cushion pad is retractably disposed on a surface of the first member. The first magnetic component is installed in the first member, and synchronously moves with the first cushion pad. The second member comprises a second magnetic component. When the first member and the second member are covered together, with the magnetic effect between the first magnetic component and the second magnetic component, the first cushion pad is linked by the first magnetic unit to protrude from or retract into the first member.
Abstract:
Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.
Abstract:
Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die.
Abstract:
A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
Abstract:
A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.