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    Scalable circuit-under-pad device topologies for lateral GaN power transistors
    31.
    发明授权
    Scalable circuit-under-pad device topologies for lateral GaN power transistors 有权

    公开(公告)号：US10529802B2

    公开(公告)日：2020-01-07

    申请号：US15988453

    申请日：2018-05-24

    Applicant: GaN Systems Inc.

    Inventor： Ahmad Mizan ,  Hossein Mousavian ,  Xiaodong Cui

    IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40

    Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

    GaN TRANSISTOR WITH INTEGRATED DRAIN VOLTAGE SENSE FOR FAST OVERCURRENT AND SHORT CIRCUIT PROTECTION
    32.
    发明申请
    GaN TRANSISTOR WITH INTEGRATED DRAIN VOLTAGE SENSE FOR FAST OVERCURRENT AND SHORT CIRCUIT PROTECTION 审中-公开

    公开(公告)号：US20190140630A1

    公开(公告)日：2019-05-09

    申请号：US15807021

    申请日：2017-11-08

    Applicant: GaN Systems Inc.

    Inventor： Di CHEN ,  Larry SPAZIANI

    IPC: H03K17/081 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

    Abstract: A GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which provides a drain voltage sense signal VDSEN. The integrated drain voltage sense circuit comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which form a resistive divider for sensing the drain voltage of SW_MAIN, and generating the drain sense voltage output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets to VDSEN=0. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate SW_MAIN by the gate driver.

    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES
    36.
    发明申请
    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES 有权
    用于大面积氮化物半导体器件的容错设计

    公开(公告)号：US20150162252A1

    公开(公告)日：2015-06-11

    申请号：US14568507

    申请日：2014-12-12

    Applicant: GAN SYSTEMS INC.

    Inventor： Gregory P. KLOWAK ,  Cameron MCKNIGHT-MACNEIL ,  Howard TWEDDLE ,  Ahmad MIZAN ,  Nigel SPRINGETT

    IPC: H01L21/66 ,  H01L29/201 ,  H01L23/528 ,  H01L29/778 ,  H01L27/095 ,  H01L29/20 ,  H01L29/205

    CPC classification number: H01L29/7787 ,  H01L22/14 ,  H01L22/22 ,  H01L22/32 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

    Abstract translation: 提供了大面积氮化物半导体器件的容错设计，便于测试和隔离缺陷区域。 晶体管包括多个岛的阵列，每个岛包括有源区，源极和漏极以及栅电极。 每个岛的电极在阵列的至少一个方向上与相邻岛的电极电隔离。 提供源极，漏极和栅极接触焊盘，以实现每个岛的电气测试。 在岛的电测试以识别有缺陷的岛之后，形成覆盖的电连接以使源电极并联连接，漏电极并联，并且互连栅电极以形成具有大栅极宽度Wg的公共栅电极。 选择性地向好的岛屿提供互连，同时电隔离有缺陷的岛屿。 这种方法使得制造大面积GaN器件（包括混合器件）在经济上是可行的。

    WAFER TESTING FOR CURRENT PROPERTY OF A POWER TRANSISTOR
    37.
    发明申请
    WAFER TESTING FOR CURRENT PROPERTY OF A POWER TRANSISTOR 有权

    公开(公告)号：US20250020712A1

    公开(公告)日：2025-01-16

    申请号：US18349780

    申请日：2023-07-10

    Applicant: GAN SYSTEMS INC.

    Inventor： Iman ABDALI MASHHADI ,  Thomas William MACELWEE ,  Mohammad BOZORGI ,  Ting-Hsiang HSU ,  Meng-ta YOU ,  Regina Inyangat AKUDO ,  Yueh Lin CHIANG

    IPC: G01R31/26

    Abstract: Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.

    SUPERLATTICE EPITAXIAL STRUCTURE WITH VARYING LATTICE PARAMETER DIFFERENCES
    40.
    发明申请
    SUPERLATTICE EPITAXIAL STRUCTURE WITH VARYING LATTICE PARAMETER DIFFERENCES 有权

    公开(公告)号：US20240379765A1

    公开(公告)日：2024-11-14

    申请号：US18315398

    申请日：2023-05-10

    Applicant: GAN SYSTEMS INC.

    Inventor： Claudio Andres Canizares

    IPC: H01L29/15 ,  H01L29/20 ,  H01L29/201

    Abstract: A superlattice epitaxial structure epitaxially grown on a substrate. The superlattice epitaxial structure includes epitaxial layers composing multiple layer sequences. Each of the multiple layer sequences includes a corresponding lower layer and a corresponding upper layer epitaxially grown on the corresponding lower layer. The lattice parameter of the epitaxial layers alternate lower and higher (or higher and lower) moving up through the superlattice epitaxial structure. The difference in lattice parameters in the neighboring lower and higher epitaxial layers may also vary moving up through the epitaxial structure. Thus, by varying the difference between the lattice parameters, the strain endured at that level may be engineered with the effect of increasing the electrical resistance seen vertically through the superlattice epitaxial structure, thus allowing the structure to be thinner and/or operate with higher voltages.

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