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    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR
    32.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR 失效
    半导体存储器件及其方法

    公开(公告)号：US20070171755A1

    公开(公告)日：2007-07-26

    申请号：US11616846

    申请日：2006-12-27

    Applicant: Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    Inventor： Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C11/406 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618

    Abstract: A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

    Abstract translation: 提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。 在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域 多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。 授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

    Semiconductor package having multiple embedded chips
    34.
    发明授权
    Semiconductor package having multiple embedded chips 有权
    具有多个嵌入式芯片的半导体封装

    公开(公告)号：US07170157B2

    公开(公告)日：2007-01-30

    申请号：US10803043

    申请日：2004-03-18

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: H01L23/02 ,  H01L23/34

    CPC classification number: H01L25/065 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014

    Abstract: A semiconductor package includes multiple embedded chips, each chip including a common circuit having substantially the same common function. The common circuit in a selected one of the chips is enabled. The common circuit in one or more other ones of the chips is disabled. As a result, the enabled common circuit performs the common function for the selected chip and the one or more other chips.

    Abstract translation: 半导体封装包括多个嵌入式芯片，每个芯片包括具有基本上相同的共同功能的公共电路。 所选择的一个芯片中的公共电路被使能。 一个或多个其他芯片中的公共电路被禁用。 结果，使能的公共电路执行所选择的芯片和一个或多个其他芯片的共同功能。

    Multi-bank dynamic random access memory devices having all bank precharge capability
    37.
    发明授权
    Multi-bank dynamic random access memory devices having all bank precharge capability 有权
    具有全部预充电能力的多组动态随机存取存储器件

    公开(公告)号：US06343036B1

    公开(公告)日：2002-01-29

    申请号：US09157271

    申请日：1998-09-18

    Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC: G11C700

    CPC classification number: G11C7/1018 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于 灭活信号在预充电循环中工作。

    Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
    38.
    发明授权
    Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation 有权
    利用时钟屏蔽信号来控制内部时钟信号产生的同步动态随机存取存储器件

    公开(公告)号：US06279116B1

    公开(公告)日：2001-08-21

    申请号：US09390220

    申请日：1999-09-03

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: G06F114

    CPC classification number: G11C7/225 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Redundancy fuse box and method for arranging the same
    39.
    发明授权
    Redundancy fuse box and method for arranging the same 失效
    冗余保险丝盒及其布置方法

    公开(公告)号：US6067268A

    公开(公告)日：2000-05-23

    申请号：US110630

    申请日：1998-07-06

    Applicant: Ho-cheol Lee

    Inventor： Ho-cheol Lee

    IPC: G11C11/413 ,  G11C11/401 ,  G11C11/41 ,  G11C29/00 ,  G11C29/04 ,  H01L27/10 ,  G11C7/00

    CPC classification number: G11C29/80 ,  G11C29/781 ,  G11C29/785

    Abstract: A redundancy fuse box of a semiconductor memory device which minimizes address line loading by organizing fuse cells into fuse cell groups sharing the same sub-address line. The address signal therefore has to traverse across a shorter distance along the semiconductor device, which contributes to a reduction in cell line loading. The redundancy fuse box includes a plurality of fuse cells, each having a transistor and fuse, to which an address signal of a memory cell is applied. The respective fuse boxes are constructed as one fuse box by being laid out in the same place. The fuse box includes a plurality of fuse cells which receive the same address signal along a common sub-address line and is wired so that outputs of the fuse cells which received the same address signal contribute to different redundancy enable signals.

    Abstract translation: 一种半导体存储器件的冗余保险丝盒，其通过将熔丝单元组织成共享相同子地址线的熔丝单元组来最小化地址线负载。 因此，地址信号必须穿过半导体器件的较短距离，这有助于细胞系负载的减少。 冗余保险丝盒包括多个熔丝单元，每个熔丝单元具有晶体管和熔丝，施加存储单元的地址信号。 各保险丝盒通过布置在同一个地方构成一个保险丝盒。 保险丝盒包括多个熔丝单元，其沿公共子地址线接收相同的地址信号，并被布线，使得接收相同地址信号的熔丝单元的输出有助于不同的冗余使能信号。

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