公开(公告)号：US6002178A

公开(公告)日：1999-12-14

申请号：US968981

申请日：1997-11-12

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/538 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L22/20 ,  H01L21/485 ,  H01L23/5382 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/4941 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: The present invention discloses a chip-size package (CSP) ready multiple chip module (MCM) board having a top surface and a bottom surface for mounting and packaging a plurality of integrated circuit (IC) chips on the top surface. The MCM board is provided with a plurality of chip connection terminals on the top surface for electrically connecting to the IC chips. The MCM board further includes a plurality of via connectors in electrical connection with each of the MCM connection terminals. The MCM board further includes a plurality of CSP connection terminals disposed on the bottom surface substantially under the IC chips wherein each of the via connectors penetrating the MCM board for electrically connecting the CSP connection terminals to the MCM connection terminals.

Abstract translation: 本发明公开了一种具有顶表面和底表面的芯片尺寸封装（CSP）就绪多芯片模块（MCM）板，用于在顶表面上安装和封装多个集成电路（IC）芯片。 MCM板在顶表面上设置有多个芯片连接端子，用于电连接到IC芯片。 MCM板还包括与每个MCM连接端子电连接的多个通孔连接器。 MCM板还包括多个CSP连接端子，其基本上设置在IC芯片的底面上，其中每个通孔连接器穿过MCM板，用于将CSP连接端子电连接到MCM连接端子。

公开(公告)号：US5300187A

公开(公告)日：1994-04-05

申请号：US940108

申请日：1992-09-03

Applicant: Israel A. Lesk ,  Young Limb ,  Philip J. Tobin ,  John Franka ,  Paul T. Lin ,  Jonathan C. Dahm ,  Gary L. Huffman ,  Bich-Yen Nguyen

Inventor： Israel A. Lesk ,  Young Limb ,  Philip J. Tobin ,  John Franka ,  Paul T. Lin ,  Jonathan C. Dahm ,  Gary L. Huffman ,  Bich-Yen Nguyen

IPC: H01L21/306 ,  B44C1/22

CPC classification number: H01L21/02046 ,  Y10S438/906

Abstract: Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.

Abstract translation: 通过将半导体材料加热到卤素化合物将分解成卤素原子的最低温度的范围内的温度而不使用紫外线照射并与存在于半导体材料上的污染物反应并且与半导体材料的最高温度 800℃，其中在半导体材料上形成小于或等于约50埃的氧化物。 其中半导体材料被加热的环境是由非反应性气体和卤素化合物组成的环境，其至少足以从半导体材料中除去大量污染物的时间。

公开(公告)号：US5247423A

公开(公告)日：1993-09-21

申请号：US887963

申请日：1992-05-26

Applicant: Paul T. Lin ,  Michael B. McShane

Inventor： Paul T. Lin ,  Michael B. McShane

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14

CPC classification number: H01L23/4985 ,  H01L23/3121 ,  H01L25/0657 ,  H01L25/105 ,  H05K1/144 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025

Abstract: A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.

公开(公告)号：US5049526A

公开(公告)日：1991-09-17

申请号：US362644

申请日：1989-06-07

Applicant: Michael B. McShane ,  Paul T. Lin

Inventor： Michael B. McShane ,  Paul T. Lin

IPC: B29C45/14 ,  H01L21/56

CPC classification number: B29C45/14655 ,  H01L21/565 ,  H01L2224/48247 ,  Y10T29/49121

Abstract: A method for fabricating and especially for encapsulating a semiconductor device in a plastic package is disclosed. In accordance with one embodiment of the invention the method includes steps of providing an encapsulation mold having a first chamber and a second chamber, with the second chamber spaced outwardly from and substantially surrounding the first chamber. The first chamber is shaped to receive a removable insert. An insert is selected for the particular body type and style which is desired and that insert is secured in the first chamber. The insert has a cavity which is shaped to define the desired encapsulated device package body. A lead frame is provided including a bonding area and a plurality of leads, each lead having a inner portion near the bonding area and an outer portion extending outwardly from the bonding area. A semiconductor device die is secured to the lead frame and the lead frame with the die attached is aligned within the encapsulation mold to place the semiconductor device die and the inner ends of the leads within the cavity defined by the inserts. The outer ends of the leads extend through the second chamber. Plastic material is then injected into the mold to form the device package body about the semiconductor device die. The package body is shaped by the cavity and the inserts and the carrier ring is shaped by the second chamber.

公开(公告)号：US4380866A

公开(公告)日：1983-04-26

申请号：US260493

申请日：1981-05-04

Applicant: Roger S. Countryman, Jr. ,  Paul T. Lin

Inventor： Roger S. Countryman, Jr. ,  Paul T. Lin

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/08 ,  H01L21/263 ,  G11C11/40 ,  H01L7/44

CPC classification number: H01L27/11266 ,  H01L27/112 ,  H01L29/0847

Abstract: A process is disclosed for fabricating a MOS ROM which allows programming of the ROM late in the process sequence. A conventional silicon gate process is used to fabricate the devices up through the step of patterning the polycrystalline silicon gate electrode. Selected devices in the array are then programmed to an off-state by fabricatng those devices with either the source or drain region offset from the gate electrode. This is accomplished by a programming mask which, together with the gate electrode, provides selective location of the source or drain regions. Devices having an offset source or drain are off-state devices, while those having a normal source and drain function conventionally and conduct when a read voltage is applied.

Abstract translation: 公开了一种用于制造MOS ROM的过程，其允许在处理顺序中较晚编程ROM。 常规的硅栅极工艺用于通过图案化多晶硅栅电极的步骤向上制造器件。 阵列中的选定器件然后通过将源极或漏极区域偏离栅极电极的器件编程为关断状态。 这通过编程掩模来实现，编程掩模与栅极电极一起提供源极或漏极区域的选择性位置。 具有偏移源或漏极的器件是截止状态器件，而具有常规源极和漏极功能的器件通常是在施加读取电压时导通的。

公开(公告)号：US5329159A

公开(公告)日：1994-07-12

申请号：US100943

申请日：1993-08-03

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/10 ,  H01L23/495 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC classification number: H05K3/3426 ,  H01L21/4842 ,  H01L23/10 ,  H01L23/49534 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H01L2924/30107 ,  H05K1/0271 ,  H05K2201/10689 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T29/49121

Abstract: A quad leadframe (22') for a CERQUAD is manufactured using conventional cladding and stamping technologies. A first metal layer (12) is provided with multiple cavities (14). A second metal layer (14) is clad to the first metal layer. A leadframe strip (22) can then be stamped from the clad metal. The leadframe has a leads (24) and bonding posts (28). The leads comprise two metal layers, and the bonding posts comprise only the second metal layer. The leadframe can then be used in the assembly of a semiconductor device (32). The portion of the leads external to the package body can be optionally etched to remove the second metal layer.

Abstract translation: 使用传统的包层和冲压技术制造用于CERQUAD的四引线框架（22'）。 第一金属层（12）设置有多个空腔（14）。 第二金属层（14）被包覆到第一金属层。 然后可以从复合金属冲压引线框条（22）。 引线框具有引线（24）和接合柱（28）。 引线包括两个金属层，并且接合柱仅包括第二金属层。 然后可以将引线框架用于半导体器件（32）的组装中。 可以任选地蚀刻包装体外部引线的部分以去除第二金属层。

公开(公告)号：US5258648A

公开(公告)日：1993-11-02

申请号：US982404

申请日：1992-11-27

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: G01R31/28 ,  H01L21/60 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34 ,  H01L23/48 ,  H01L23/02 ,  H02B1/00 ,  H05K1/00

CPC classification number: G01R31/2863 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/284 ,  H05K3/3431 ,  Y10S439/912

Abstract: A composite flip chip semiconductor device (10) permits burn-in testing and rework to be performed on the device while also enhancing electrical, thermal, and mechanical device performance. The device includes a semiconductor die (12) having a plurality of bonding pads (14). Also included in the composite device is an interposer (22) having a first surface with a plurality of traces (26). A plurality of vias (24) extend from the first surface of the interposer (22) to a second surface. The semiconductor die (12) is electrically coupled to the plurality of vias of the interposer which in turn is to be coupled to a substrate.

Abstract translation: 复合倒装芯片半导体器件（10）允许在器件上执行老化测试和返工，同时还提高电气，热和机械器件性能。 该器件包括具有多个接合焊盘（14）的半导体管芯（12）。 还包括在复合器件中的是具有多个迹线（26）的第一表面的插入器（22）。 多个通孔（24）从插入件（22）的第一表面延伸到第二表面。 半导体管芯（12）电耦合到插入器的多个通孔，该通孔又与衬底耦合。

公开(公告)号：US5239198A

公开(公告)日：1993-08-24

申请号：US907970

申请日：1992-07-02

Applicant: Paul T. Lin ,  Michael B. McShane

Inventor： Paul T. Lin ,  Michael B. McShane

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49855 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K3/3431 ,  Y10T29/49146

Abstract: A low cost manufacturing method is used to fabricate a small multiple chip semiconductor device (10). In one embodiment, a first pattern of conductive traces (14) is formed on one surface of a substrate (12), and a second pattern of traces (16) is formed on a second surface of the substrate (12). A first semiconductor die (20) is interconnected to the first traces (14), and a package body (24) is formed around the first die and a portion of the traces. A second semiconductor die (26) is interconnected to the second traces (16) on the second surface. A second package body (28) is formed around the second die and a portion of the traces (16). Solder balls (32) are coupled to exposed portions of the second traces (16) around the perimeter of the package body (28) to establish external power and ground connections to each die. Edge leads (36) are externally soldered to the traces (14 & 16) around the periphery of the substrate (12) to establish remaining electrical connections.

Abstract translation: 使用低成本制造方法来制造小型多芯片半导体器件（10）。 在一个实施例中，在衬底（12）的一个表面上形成导电迹线（14）的第一图案，并且在衬底（12）的第二表面上形成第二迹线（16）。 第一半导体管芯（20）与第一迹线（14）互连，并且围绕第一管芯和一部分迹线形成封装主体（24）。 第二半导体管芯（26）与第二表面上的第二迹线（16）互连。 围绕第二管芯和迹线（16）的一部分形成第二封装体（28）。 焊球（32）围绕封装主体（28）的周边耦合到第二迹线（16）的暴露部分，以建立到每个管芯的外部电源和接地连接。 边缘引线（36）被外部焊接到围绕基板（12）周边的迹线（14和16）上，以建立剩余的电连接。

公开(公告)号：US5222014A

公开(公告)日：1993-06-22

申请号：US844075

申请日：1992-03-02

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L25/18 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H05K1/14

CPC classification number: H05K1/144 ,  H01L23/3121 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  Y10T29/49144 ,  Y10T29/53174

Abstract: A stackable three-dimensional multi-chip module (MCM) is provided whereby each level of chip carrier is interconnected to another level of chip carrier through reflowing of solder balls pre-bumped onto each carrier. Each level of chip carrier, except for the top carrier, has solder balls on both top and bottom surfaces of the substrate. Optional lids can be used to seal each device, and the lid height would serve as a natural positive stand-off between each level of carriers, giving rise to hour glass shaped solder joints which maximizes the fatigue life of the joints. Heat sinks to further enhance heat dissipation of the MCM can be easily accommodated in this stacking approach. Furthermore, each substrate is capable of carrying multiple chips, so the module incorporates planar chip density growth concurrently with the three-dimensional growth giving rise to an ultradense MCM.

公开(公告)号：US5200362A

公开(公告)日：1993-04-06

申请号：US756952

申请日：1991-09-09

Applicant: Paul T. Lin ,  Michael B. McShane ,  Sugio Uchida ,  Takehi Sato

Inventor： Paul T. Lin ,  Michael B. McShane ,  Sugio Uchida ,  Takehi Sato

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49855 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K3/3431 ,  Y10T29/49146

Abstract: A semiconductor device and a method for its fabrication are disclosed. In a preferred embodiment, a pattern of conductive traces is formed on a film of transfer material. A semiconductor device die is interconnected to the pattern of conductive traces and a resin body is formed around the die, one side of the conductive traces, and the interconnecting means. The film of transfer material forms, at this stage of the process, one side of the package. The film of transfer material is then peeled from the pattern of conductive traces and the resin body to expose the other side of the pattern of conductive traces. Contact to the other side of the pattern provides electrical contact to the senmiconductor device die.

Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，在转印材料的膜上形成导电迹线图案。 半导体器件裸片与导电迹线的图案互连，并且在裸片周围形成树脂体，导电迹线的一侧和互连装置。 在该过程的这个阶段，转印材料膜形成包装的一侧。 然后将转印材料的膜从导电迹线和树脂体的图案剥离，以暴露导电迹线图案的另一侧。 与图案的另一侧的接触提供与半导体器件裸片的电接触。