Chip scale surface mount package for semiconductor device and process of fabricating the same

    公开(公告)号:US06441475B2

    公开(公告)日:2002-08-27

    申请号:US09733823

    申请日:2000-12-08

    IPC分类号: H01L2302

    摘要: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed. A metal layer is sputtered or evaporated on one side of the stack; the stack is turned over and a similar process is performed on the other side of the stack. The resulting metal layers are deposited on front side of the die and extend along the edges of the die to the edges and back side of the substrate. The metal is not deposited on the surfaces of the overcoat. The strips in the stack are then separated, and the saw cuts in the perpendicular direction are broken to separate the individual dice. A thick metal layer is plated on the sputtered or evaporated layers to establish a good electrical connection between the front side and the terminal on the back side of each die. The resulting package thus includes a metal layer which wraps around the edges of the die to form an electrical connection between a location on the front side of the die and the conductive substrate. The package is essentially the same size as the die. In an alternative embodiment, a nonconductive substrate is used and vias are formed in the substrate and filled with metal to make electrical contact with the terminal on the back side of the die.

    Process of fabricating a chip scale surface mount package for semiconductor device

    公开(公告)号:US06271060B1

    公开(公告)日:2001-08-07

    申请号:US09395095

    申请日:1999-09-13

    IPC分类号: H01L2144

    摘要: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed. A metal layer is sputtered or evaporated on one side of the stack; the stack is turned over and a similar process is performed on the other side of the stack. The resulting metal layers are deposited on front side of the die and extend along the edges of the die to the edges and back side of the substrate. The metal is not deposited on the surfaces of the overcoat. The strips in the stack are then separated, and the saw cuts in the perpendicular direction are broken to separate the individual dice. A thick metal layer is plated on the sputtered or evaporated layers to establish a good electrical connection between the front side and the terminal on the back side of each die. The resulting package thus includes a metal layer which wraps around the edges of the die to form an electrical connection between a location on the front side of the die and the conductive substrate. The package is essentially the same size as the die. In an alternative embodiment, a nonconductive substrate is used and vias are formed in the substrate and filled with metal to make electrical contact with the terminal on the back side of the die.

    Shared current loop, multiple field apparatus and process for plasma
processing
    35.
    发明授权
    Shared current loop, multiple field apparatus and process for plasma processing 失效
    共享电流回路,多场仪器和等离子体处理工艺

    公开(公告)号:US4738761A

    公开(公告)日:1988-04-19

    申请号:US916007

    申请日:1986-10-06

    CPC分类号: H01J37/3405

    摘要: A shared current loop, multiple field apparatus and process for magnetron gas discharge processing is disclosed. The apparatus includes an evacuable chamber for containing a reactant gas. A multi-part cathode associated with a current loop generates multiple, independent electrical fields. The cathode comprises a first cathode portion for generating a first electric field that forms a gas discharge including ions. The second cathode portion generates a second, independent electric field. The second electric field extracts ions from the gas discharge, and may also control the energy with which the extracted ions strike an item to be processed. Each cathode portion is electrically insulated from the other and may be connected to a separate power source.